Make test and examples compile

But calibration hangs

Author: Sh3Rm4n

examples/adc.rs

@@ -20,20 +20,18 @@ fn main() -> ! {
     let clocks = rcc.cfgr.freeze(&mut dp.FLASH.constrain().acr);
 
     // set up adc1
-    let mut adc1 = adc::Adc::adc1(
+    let mut adc = adc::Adc::new(
         dp.ADC1, // The ADC we are going to control
         // The following is only needed to make sure the clock signal for the ADC is set up
         // correctly.
-        &mut dp.ADC1_2,
-        &mut rcc.ahb,
-        adc::ClockMode::default(),
         clocks,
+        &mut rcc.ahb,
     );
 
     // Set up pin PA0 as analog pin.
     // This pin is connected to the user button on the stm32f3discovery board.
     let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
-    let mut adc1_in1_pin = gpioa.pa0.into_analog(&mut gpioa.moder, &mut gpioa.pupdr);
+    let mut analog_pin = gpioa.pa0.into_analog(&mut gpioa.moder, &mut gpioa.pupdr);
 
     // Be aware that the values in the table below depend on the input of VREF.
     // To have a stable VREF input, put a condensator and a volt limiting diode in front of it.
@@ -54,8 +52,8 @@ fn main() -> ! {
     ").expect("Error using hprintln.");
 
     loop {
-        let adc1_in1_data: u16 = adc1.read(&mut adc1_in1_pin).expect("Error reading adc1.");
-        hprintln!("PA0 reads {}", adc1_in1_data).ok();
+        let adc_data: u16 = adc.read(&mut analog_pin).expect("Error reading adc1.");
+        hprintln!("PA0 reads {}", adc_data).ok();
         asm::delay(2_000_000);
     }
 }

src/adc.rs

@@ -44,7 +44,6 @@ pub struct Adc<ADC> {
     /// ADC Register
     adc: ADC,
     clocks: Clocks,
-    clock_mode: ClockMode,
     operation_mode: Option<OperationMode>,
 }
 
@@ -124,39 +123,6 @@ pub enum OperationMode {
     OneShot,
 }
 
-#[derive(Clone, Copy, PartialEq)]
-/// ADC Clock Mode
-// TODO: Add Asynchronous mode
-#[non_exhaustive]
-pub enum ClockMode {
-    // /// Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
-    // Asynchronous,
-    /// Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
-    SyncDiv1,
-    /// Use AHB clock rcc_hclk3 divided by 2
-    SyncDiv2,
-    /// Use AHB clock rcc_hclk3 divided by 4
-    SyncDiv4,
-}
-
-impl Default for ClockMode {
-    fn default() -> Self {
-        ClockMode::SyncDiv2
-    }
-}
-
-// ADC3_2 returns a pointer to a adc1_2 type, so this from is ok for both.
-impl From<ClockMode> for CKMODE_A {
-    fn from(clock_mode: ClockMode) -> Self {
-        match clock_mode {
-            //ClockMode::Asynchronous => CKMODE_A::ASYNCHRONOUS,
-            ClockMode::SyncDiv1 => CKMODE_A::SYNCDIV1,
-            ClockMode::SyncDiv2 => CKMODE_A::SYNCDIV2,
-            ClockMode::SyncDiv4 => CKMODE_A::SYNCDIV4,
-        }
-    }
-}
-
 /// ADC data register alignment
 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -311,22 +277,27 @@ where
     ///
     pub fn new(
         adc: ADC,
-        frequency: impl Into<Generic<u32>>,
+        // TODO: frequency is not a possible input
+        // Frequency can not be set per ADC peripheral, and therefor
+        // is no option for Adc::new()
+        // This has doe be configured with an external function,
+        // and thus is maye a candidate for a more general RccClocksManangement thingy.
+        // frequency: impl Into<Generic<u32>>,
+        clocks: Clocks,
         // adc_shared : &mut <ADC as Instance>::SharedInstance,
         ahb: &mut AHB,
-        clocks: Clocks,
     ) -> Self {
         let mut adc = Self {
             adc,
             clocks,
-            clock_mode: ClockMode::SyncDiv1,
             operation_mode: None,
         };
 
         // if !(adc.clocks_welldefined(clocks)) {
         //     crate::panic!("Clock settings not well defined");
         // }
 
+
         ADC::enable_clock(ahb);
         // if !(ADC::enable_clock(ahb)){
         //     crate::panic!("Clock already enabled with a different setting");
@@ -340,7 +311,7 @@ where
         // ADEN bit cannot be set during ADCAL=1
         // and 4 ADC clock cycle after the ADCAL
         // bit is cleared by hardware
-        adc.wait_adc_clk_cycles(4);
+        adc.wait_adc_clk_cycles(4, clocks);
         adc.enable();
 
         adc
@@ -440,18 +411,15 @@ where
             .modify(|_, w| w.adcaldif().single_ended().adcal().calibration());
 
         while self.adc.cr.read().adcal().is_calibration() {}
+        defmt::info!("{}", &"hi");
     }
 
-    fn wait_adc_clk_cycles(&self, cycles: u32) {
-        // using a match statement here so compilation will fail once asynchronous clk
-        // mode is implemented (CKMODE[1:0] = 00b).  This will force whoever is working
-        // on it to rethink what needs to be done here :)
-        let adc_per_cpu_cycles = match self.clock_mode {
-            ClockMode::SyncDiv1 => 1,
-            ClockMode::SyncDiv2 => 2,
-            ClockMode::SyncDiv4 => 4,
-        };
-        asm::delay(adc_per_cpu_cycles * cycles);
+    fn wait_adc_clk_cycles(&self, cycles: u32, clocks: Clocks) {
+        let frequency = ADC::clock(&clocks);
+        let cpu_cycles = cycles * clocks.sysclk().0 / frequency.0;
+        defmt::info!("{}", cpu_cycles);
+
+        asm::delay(cpu_cycles);
     }
 
     fn advregen_enable(&mut self) {

testsuite/tests/adc.rs

@@ -34,7 +34,6 @@ mod tests {
     #[init]
     fn init() -> State {
         let mut dp = unwrap!(pac::Peripherals::take());
-
         let mut rcc = dp.RCC.constrain();
         let mut flash = dp.FLASH.constrain();
         let clocks = rcc.cfgr.freeze(&mut flash.acr);
@@ -48,12 +47,10 @@ mod tests {
         };
 
         State {
-            adc: Some(adc::Adc::adc1(
+            adc: Some(adc::Adc::new(
                 dp.ADC1,
-                &mut dp.ADC1_2,
-                &mut rcc.ahb,
-                adc::ClockMode::default(),
                 clocks,
+                &mut rcc.ahb,
             )),
             analog: pair.0,
             output: pair.1,
@@ -90,12 +87,10 @@ mod tests {
         let adc1 = adc.free();
 
         defmt::debug!("Reconfigure");
-        let new_adc = adc::Adc::adc1(
+        let new_adc = adc::Adc::new(
             adc1,
-            &mut state.adc1_2,
-            &mut state.ahb,
-            adc::ClockMode::default(),
             state.clocks,
+            &mut state.ahb,
         );
 
         defmt::debug!("Replace");