Add timer test

Author: Sh3Rm4n

testsuite/Cargo.toml

@@ -19,6 +19,10 @@ harness = false
 name = "rcc"
 harness = false
 
+[[test]]
+name = "timer"
+harness = false
+
 [[test]]
 name = "gpio_input"
 harness = false

testsuite/tests/timer.rs

@@ -0,0 +1,124 @@
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use defmt_rtt as _;
+use panic_probe as _;
+
+use stm32f3xx_hal as hal;
+
+use hal::rcc::{Clocks, APB1};
+use hal::timer::{Event, Instance, MonoTimer, Timer};
+use hal::{interrupt, pac, prelude::*};
+
+use pac::TIM2;
+
+struct State {
+    timer: Option<Timer<TIM2>>,
+    mono_timer: MonoTimer,
+    clocks: Clocks,
+    apb1: APB1,
+}
+
+static INTERRUPT_FIRED: AtomicBool = AtomicBool::new(false);
+
+#[defmt_test::tests]
+mod tests {
+    use super::*;
+    use defmt::{self, assert, unwrap};
+    use hal::time::fixed_point::FixedPoint;
+
+    #[init]
+    fn init() -> State {
+        let mut cp = unwrap!(pac::CorePeripherals::take());
+        let dp = unwrap!(pac::Peripherals::take());
+
+        let mut rcc = dp.RCC.constrain();
+        let mut flash = dp.FLASH.constrain();
+        let clocks = rcc.cfgr.freeze(&mut flash.acr);
+
+        // Let's use a timer, which is avaliable for every chip
+        let timer = Timer::new(dp.TIM2, 1.Hz(), clocks, &mut rcc.apb1);
+        let mono_timer = MonoTimer::new(cp.DWT, clocks, &mut cp.DCB);
+
+        assert!(mono_timer.frequency() == clocks.hclk());
+
+        unsafe { cortex_m::peripheral::NVIC::unmask(timer.nvic()) };
+
+        State {
+            timer: Some(timer),
+            mono_timer,
+            clocks,
+            apb1: rcc.apb1,
+        }
+    }
+
+    #[test]
+    fn test_stop_and_free(state: &mut State) {
+        let timer = state.timer.take().unwrap().free();
+
+        let timer = Timer::new(timer, 100.Hz(), state.clocks, &mut state.apb1);
+
+        state.timer = Some(timer);
+    }
+
+    #[test]
+    fn test_delay(state: &mut State) {
+        let mut timer = unwrap!(state.timer.take());
+        defmt::trace!("{}", state.mono_timer);
+        let freqcyc = state.mono_timer.frequency().integer();
+
+        let instant = state.mono_timer.now();
+        timer.start(1.Hz());
+        assert!(!timer.is_event_triggered(Event::Update));
+        unwrap!(nb::block!(timer.wait()).ok());
+        let elapsed = instant.elapsed();
+
+        defmt::info!("elapsed: {}", elapsed);
+        // TODO: Test multiple frequencies and change the cycle counter window to a percentage
+        // to measure the overhead of start?
+        assert!(((freqcyc - 1000)..(freqcyc + 1000)).contains(&elapsed));
+
+        state.timer = Some(timer);
+    }
+
+    // TODO(Sh3Rm4n): For that we have to introduce a new API. (Maybe Centihertz or Something?)
+    // #[test]
+    // fn test_delay_longer_then_second(state: &mut State) {
+
+    // }
+
+    #[test]
+    fn test_interrupt(state: &mut State) {
+        let mut timer = unwrap!(state.timer.take());
+
+        assert!(!INTERRUPT_FIRED.load(Ordering::SeqCst));
+        timer.enable_interrupt(Event::Update);
+        timer.start(100_000.Hz());
+
+        while !INTERRUPT_FIRED.load(Ordering::SeqCst) {}
+
+        assert!(timer.is_event_triggered(Event::Update));
+        timer.clear_event(Event::Update);
+        assert!(!timer.is_event_triggered(Event::Update));
+
+        state.timer = Some(timer);
+    }
+}
+
+#[interrupt]
+fn TIM2() {
+    INTERRUPT_FIRED.store(true, Ordering::SeqCst);
+
+    // Make it easy on ourselfs and just disable all interrupts.
+    // This way, the interrupt rountine dooes not have to have access to the timer peripheral,
+    // which would mean to access the internally managed state of the test module,
+    // which can't be accessed right now.
+    //
+    // This is all needed, to clear the fired interrupt.
+    assert!(cortex_m::peripheral::NVIC::is_active(
+        <pac::TIM2 as Instance>::INTERRUPT
+    ));
+    cortex_m::peripheral::NVIC::mask(<pac::TIM2 as Instance>::INTERRUPT);
+}