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Extend documentation on clock cfgr behavior
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src/rcc.rs

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@@ -373,6 +373,11 @@ impl CFGR {
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}
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/// Sets a frequency for the `APB1` bus
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///
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/// - Maximal supported frequency: 36 Mhz
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///
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/// If not manually set, it will be set to [`CFGR::sysclk`] frequency
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/// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz
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pub fn pclk1<F>(mut self, freq: F) -> Self
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where
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F: Into<Hertz>,
@@ -382,6 +387,16 @@ impl CFGR {
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}
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/// Sets a frequency for the `APB2` bus
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///
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/// # Resolution and Limits
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///
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/// Following is true for devices **except**, as these allow finer resolutions
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/// even when using the internal oscillator:
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///
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/// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
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///
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/// - Maximal supported frequency with HSE: 72 Mhz
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/// - Maximal supported frequency without HSE: 64 Mhz
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pub fn pclk2<F>(mut self, freq: F) -> Self
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where
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F: Into<Hertz>,
@@ -391,6 +406,19 @@ impl CFGR {
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}
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/// Sets the system (core) frequency
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///
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/// # Resolution and Limits
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///
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/// Following is true for devices **except**, as these allow finer resolutions
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/// even when using the internal oscillator:
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///
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/// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
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///
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/// - Maximal supported frequency with `HSE`: 72 Mhz
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/// - Maximal supported frequency without `HSE`: 64 Mhz
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///
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/// If [`CFGR::hse`] is not used, therefor `HSI / 2` is used.
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/// Only multiples of (HSI / 2) (4 Mhz) are allowed.
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pub fn sysclk<F>(mut self, freq: F) -> Self
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where
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F: Into<Hertz>,
@@ -772,6 +800,14 @@ impl Clocks {
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}
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/// Returns whether the USBCLK clock frequency is valid for the USB peripheral
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///
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/// If the micrcontroller does support USB, 48 Mhz or 72 Mhz have to be used
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/// and the [`CFGR::hse`] must be used.
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///
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/// The APB1 / [`CFGR::pclk1`] clock must have a minimum frequency of 10 MHz to avoid data
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/// overrun/underrun problems. [RM0316 32.5.2][RM0316]
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///
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/// [RM0316]: https://www.st.com/resource/en/reference_manual/dm00043574.pdf
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pub fn usbclk_valid(&self) -> bool {
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self.usbclk_valid
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}

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