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Remove cast in favor of core::convert
1 parent 53d75f3 commit 9511817

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5 files changed

+23
-27
lines changed

5 files changed

+23
-27
lines changed

Cargo.toml

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,10 +41,6 @@ optional = true
4141
version = "0.2"
4242
features = ["const-fn"]
4343

44-
[dependencies.cast]
45-
version = "0.2"
46-
default-features = false
47-
4844
[dependencies.stm32-usbd]
4945
version = "0.5"
5046
optional = true

src/delay.rs

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
//! Delays
22
3-
use cast::u32;
3+
use core::convert::From;
4+
45
use cortex_m::peripheral::syst::SystClkSource;
56
use cortex_m::peripheral::SYST;
67

@@ -35,13 +36,13 @@ impl DelayMs<u32> for Delay {
3536

3637
impl DelayMs<u16> for Delay {
3738
fn delay_ms(&mut self, ms: u16) {
38-
self.delay_ms(u32(ms));
39+
self.delay_ms(u32::from(ms));
3940
}
4041
}
4142

4243
impl DelayMs<u8> for Delay {
4344
fn delay_ms(&mut self, ms: u8) {
44-
self.delay_ms(u32(ms));
45+
self.delay_ms(u32::from(ms));
4546
}
4647
}
4748

@@ -63,12 +64,12 @@ impl DelayUs<u32> for Delay {
6364

6465
impl DelayUs<u16> for Delay {
6566
fn delay_us(&mut self, us: u16) {
66-
self.delay_us(u32(us))
67+
self.delay_us(u32::from(us))
6768
}
6869
}
6970

7071
impl DelayUs<u8> for Delay {
7172
fn delay_us(&mut self, us: u8) {
72-
self.delay_us(u32(us))
73+
self.delay_us(u32::from(us))
7374
}
7475
}

src/dma.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ use crate::{
1212
rcc::AHB,
1313
serial,
1414
};
15-
use cast::u16;
1615
use core::{
16+
convert::TryFrom,
1717
mem,
1818
sync::atomic::{self, Ordering},
1919
};
@@ -57,7 +57,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
5757
// method we can call is `write_buffer`, which is allowed by
5858
// `WriteBuffer`'s safety requirements.
5959
let (ptr, len) = unsafe { buffer.write_buffer() };
60-
let len = u16(len).expect("buffer is too large");
60+
let len = u16::try_from(len).expect("buffer is too large");
6161

6262
// NOTE(unsafe) We are using the address of a 'static WriteBuffer here,
6363
// which is guaranteed to be safe for DMA.
@@ -84,7 +84,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
8484
// `&mut self` methods we can call, so we are safe according to
8585
// `ReadBuffer`'s safety requirements.
8686
let (ptr, len) = unsafe { buffer.read_buffer() };
87-
let len = u16(len).expect("buffer is too large");
87+
let len = u16::try_from(len).expect("buffer is too large");
8888

8989
// NOTE(unsafe) We are using the address of a 'static ReadBuffer here,
9090
// which is guaranteed to be safe for DMA.

src/i2c.rs

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,14 @@
11
//! Inter-Integrated Circuit (I2C) bus
22
3+
use core::convert::TryFrom;
4+
35
use crate::{
46
gpio::{gpioa, gpiob, gpiof, AF4},
57
hal::blocking::i2c::{Read, Write, WriteRead},
68
pac::{I2C1, I2C2},
79
rcc::{Clocks, APB1},
810
time::Hertz,
911
};
10-
use cast::u8;
1112

1213
/// I2C error
1314
#[derive(Debug)]
@@ -152,28 +153,25 @@ macro_rules! hal {
152153
(presc, scll, sclh, sdadel, scldel)
153154
};
154155

155-
let presc = u8(presc).unwrap();
156156
assert!(presc < 16);
157-
let scldel = u8(scldel).unwrap();
158157
assert!(scldel < 16);
159-
let sdadel = u8(sdadel).unwrap();
160158
assert!(sdadel < 16);
161-
let sclh = u8(sclh).unwrap();
162-
let scll = u8(scll).unwrap();
159+
let sclh = u8::try_from(sclh).unwrap();
160+
let scll = u8::try_from(scll).unwrap();
163161

164162
// Configure for "fast mode" (400 KHz)
165163
// NOTE(write): writes all non-reserved bits.
166164
i2c.timingr.write(|w| {
167165
w.presc()
168-
.bits(presc)
166+
.bits(presc as u8)
167+
.sdadel()
168+
.bits(sdadel as u8)
169+
.scldel()
170+
.bits(scldel as u8)
169171
.scll()
170172
.bits(scll)
171173
.sclh()
172174
.bits(sclh)
173-
.sdadel()
174-
.bits(sdadel)
175-
.scldel()
176-
.bits(scldel)
177175
});
178176

179177
// Enable the peripheral

src/timer.rs

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
//! Timers
22
3+
use core::convert::{From, TryFrom};
4+
35
use crate::hal::timer::{CountDown, Periodic};
46
#[cfg(any(
57
feature = "stm32f301",
@@ -49,7 +51,6 @@ use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6};
4951
))]
5052
use crate::pac::{TIM3, TIM7};
5153

52-
use cast::{u16, u32};
5354
use void::Void;
5455

5556
use crate::rcc::{Clocks, APB1, APB2};
@@ -99,16 +100,16 @@ macro_rules! hal {
99100
let timer_clock = $TIMX::get_clk(&self.clocks);
100101
let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
101102
/ frequency;
102-
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
103+
let psc = u16::try_from((ticks - 1) / (1 << 16)).unwrap();
103104

104105
// NOTE(write): uses all bits in this register.
105106
self.tim.psc.write(|w| w.psc().bits(psc));
106107

107-
let arr = u16(ticks / u32(psc + 1)).unwrap();
108+
let arr = u16::try_from(ticks / u32::from(psc + 1)).unwrap();
108109

109110
// TODO (sh3rm4n)
110111
// self.tim.arr.write(|w| { w.arr().bits(arr) });
111-
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
112+
self.tim.arr.write(|w| unsafe { w.bits(u32::from(arr)) });
112113

113114
// Trigger an update event to load the prescaler value to the clock
114115
// NOTE(write): uses all bits in this register.

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