rcc: Add force pll use function

Author: Sh3Rm4n

CHANGELOG.md

@@ -61,6 +61,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   - On the bases of these interrupts, the interrupt controller (NVIC) can
     be set to mask or unmask these interrupts.
 - Implement the `embedded-hal::timer::Cancel` trait for timers. ([#267])
+- Add `use_pll` to `CFGR` - the clock configuration - to force to use the PLL
+  source for the systemclock. Also `Clocks::pllclk()` was introduced to be able
+  to check, whether PLL is used.
 
 [`enumset`]: https://crates.io/crates/enumset
 

src/rcc.rs

@@ -261,17 +261,32 @@ impl BDCR {
 /// let rcc = dp.RCC.constrain();
 /// use_cfgr(&mut rcc.cfgr)
 /// ```
-#[derive(Default)]
 pub struct CFGR {
     hse: Option<u32>,
     hse_bypass: bool,
+    pll_bypass: bool,
     css: bool,
     hclk: Option<u32>,
     pclk1: Option<u32>,
     pclk2: Option<u32>,
     sysclk: Option<u32>,
 }
 
+impl Default for CFGR {
+    fn default() -> Self {
+        Self {
+            hse: None,
+            hse_bypass: false,
+            pll_bypass: true,
+            css: false,
+            hclk: None,
+            pclk1: None,
+            pclk2: None,
+            sysclk: None,
+        }
+    }
+}
+
 pub(crate) struct PllConfig {
     src: cfgr::PLLSRC_A,
     mul: cfgr::PLLMUL_A,
@@ -350,6 +365,12 @@ impl CFGR {
         self
     }
 
+    /// Set this to disallow bypass the PLLCLK for the systemclock generation.
+    pub fn use_pll(mut self) -> Self {
+        self.pll_bypass = false;
+        self
+    }
+
     /// Enable `HSE` bypass.
     ///
     /// Uses user provided clock signal instead of an external oscillator.
@@ -602,9 +623,11 @@ impl CFGR {
             // because the two valid USB clocks, 72 Mhz and 48 Mhz, can't be generated
             // directly from neither the internal rc (8 Mhz)  nor the external
             // Oscillator (max 32 Mhz), without using the PLL.
-            (Some(sysclk), Some(hse)) if sysclk == hse => (hse, cfgr::SW_A::HSE, None),
+            (Some(sysclk), Some(hse)) if sysclk == hse && self.pll_bypass => {
+                (hse, cfgr::SW_A::HSE, None)
+            }
             // No need to use the PLL
-            (Some(sysclk), None) if sysclk == HSI.integer() => {
+            (Some(sysclk), None) if sysclk == HSI.integer() && self.pll_bypass => {
                 (HSI.integer(), cfgr::SW_A::HSI, None)
             }
             (Some(sysclk), _) => {
@@ -758,6 +781,7 @@ impl CFGR {
             ppre2,
             sysclk: Hertz(sysclk),
             usbclk_valid,
+            pll_bypass: self.pll_bypass,
         }
     }
 }
@@ -775,6 +799,7 @@ pub struct Clocks {
     ppre2: u8,
     sysclk: Hertz,
     usbclk_valid: bool,
+    pll_bypass: bool,
 }
 
 // TODO(Sh3Rm4n) Add defmt support for embedded-time!
@@ -784,14 +809,15 @@ impl defmt::Format for Clocks {
         // Format as hexadecimal.
         defmt::write!(
             f,
-            "Clocks {{ hclk: {} Hz, pclk1: {} Hz, pclk2: {} Hz, ppre1: {:b}, ppre2: {:b}, sysclk: {} Hz, usbclk_valid: {} }}",
+            "Clocks {{ hclk: {} Hz, pclk1: {} Hz, pclk2: {} Hz, ppre1: {:b}, ppre2: {:b}, sysclk: {} Hz, usbclk_valid: {}, pll_bypass: {} }}",
             self.hclk.integer(),
             self.pclk1.integer(),
             self.pclk2.integer(),
             self.ppre1,
             self.ppre2,
             self.sysclk.integer(),
             self.usbclk_valid,
+            self.pll_bypass,
         );
     }
 }
@@ -830,6 +856,19 @@ impl Clocks {
         self.sysclk
     }
 
+    /// Returns the PLL clock if configured, else it returns `None`.
+    ///
+    /// The PLL clock is a source of the system clock, but it is not necessarily configured to be one.
+    pub fn pllclk(&self) -> Option<Hertz> {
+        if self.pll_bypass {
+            None
+        } else {
+            // The PLLCLK is the same as the sysclk, beccause
+            // the sysclk is using it as a source.
+            Some(self.sysclk())
+        }
+    }
+
     /// Returns whether the USBCLK clock frequency is valid for the USB peripheral
     ///
     /// If the microcontroller does support USB, 48 Mhz or 72 Mhz have to be used

src/timer.rs

@@ -472,15 +472,15 @@ macro_rules! timer_var_clock {
                             clocks.$pclkX()
                         }
                     }
-                    // TODO: Implement PLL in Rcc
-                    // 1: PLL vco output (running up to 144 MHz)
-                    // TODO: Make sure that * 2 is always correct
-                    crate::pac::rcc::cfgr3::TIM1SW_A::PLL /* if $PLL */ => clocks.$pclkX() * 2,
-                    // This state should not be posslbe.
-                    // TODO: Check if this assumption is correct.
-                    // TODO: Because of the way the it is created in the macro,
-                    // // this disticntion is not really needed anymore?
-                    // _ => crate::panic!("Invalid timer clock source."),
+                    crate::pac::rcc::cfgr3::TIM1SW_A::PLL => {
+                        if let Some(pllclk) = clocks.pllclk() {
+                            pllclk * 2
+                        } else {
+                            // This state should currently not be possible,
+                            // because the software source can not be configured right now.
+                            crate::panic!("Invalid timer clock source.");
+                        }
+                    }
                 }
             }
         )+