Adc Refactor

Author: Sh3Rm4n

src/adc.rs

@@ -12,15 +12,14 @@
 use cortex_m::asm;
 use embedded_hal::adc::{Channel, OneShot};
 
-use crate::{
-    gpio::{self, Analog},
-    pac::{
-        adc1::{cfgr::ALIGN_A, smpr1::SMP9_A, smpr2::SMP18_A},
-        adc1_2::ccr::CKMODE_A,
-        ADC1, ADC1_2, ADC2,
-    },
-    rcc::{Clocks, AHB},
+use crate::gpio::{self, Analog};
+use crate::pac::{
+    adc1::{cfgr::ALIGN_A, smpr1::SMP9_A, smpr2::SMP18_A},
+    adc1_2::ccr::CKMODE_A,
+    ADC1, ADC1_2, ADC2, ADC3_4,
 };
+use crate::pac::{adc1, adc1_2};
+use crate::rcc::{Clocks, AHB};
 
 #[cfg(any(
     feature = "stm32f303xb",
@@ -108,6 +107,8 @@ impl From<SampleTime> for SMP18_A {
     }
 }
 
+impl
+
 /// ADC operation mode
 // TODO: Implement other modes (DMA, Differential,…)
 // TODO(Sh3Rm4n): Maybe make operation modes to type states to better
@@ -313,32 +314,34 @@ macro_rules! adc_hal {
                 ///
                 pub fn $adcx(
                     adc: $ADC,
+                    frequency: impl Into<Generic<u32>>,
                     adc_common : &mut $ADC_COMMON,
                     ahb: &mut AHB,
-                    clock_mode: ClockMode,
                     clocks: Clocks,
                 ) -> Self {
-                    let mut this_adc = Self {
+                    let mut adc = Self {
                         adc,
                         clocks,
-                        clock_mode,
-                        operation_mode: None,
                     };
-                    if !(this_adc.clocks_welldefined(clocks)) {
+                    if !(adc.clocks_welldefined(clocks)) {
                         crate::panic!("Clock settings not well defined");
                     }
-                    if !(this_adc.enable_clock(ahb, adc_common)){
+                    if !(adc.enable_clock(ahb, adc_common)){
                         crate::panic!("Clock already enabled with a different setting");
                     }
-                    this_adc.set_align(Align::default());
-                    this_adc.calibrate();
+
+                    common.ccr.modify(|_, w| w
+                        .ckmode().variant(self.clock_mode.into())
+                    );
+                    adc.set_align(Align::default());
+                    adc.calibrate();
                     // ADEN bit cannot be set during ADCAL=1
                     // and 4 ADC clock cycle after the ADCAL
                     // bit is cleared by hardware
-                    this_adc.wait_adc_clk_cycles(4);
-                    this_adc.enable();
+                    adc.wait_adc_clk_cycles(4);
+                    adc.enable();
 
-                    this_adc
+                    adc
                 }
 
                 /// Releases the ADC peripheral and associated pins
@@ -422,10 +425,10 @@ macro_rules! adc_hal {
                 }
 
                 /// Calibrate according to RM0316 15.3.8
-                fn calibrate(&mut self) {
+                fn calibrate(&mut self, clocks: Clocks) {
                     if !self.adc.cr.read().advregen().is_enabled() {
                         self.advregen_enable();
-                        self.wait_advregen_startup();
+                        self.wait_advregen_startup(clocks);
                     }
 
                     self.disable();
@@ -458,8 +461,8 @@ macro_rules! adc_hal {
                 /// wait for the advregen to startup.
                 ///
                 /// This is based on the MAX_ADVREGEN_STARTUP_US of the device.
-                fn wait_advregen_startup(&self) {
-                    asm::delay((MAX_ADVREGEN_STARTUP_US * 1_000_000) / self.clocks.sysclk().0);
+                fn wait_advregen_startup(&self, clocks: Clocks) {
+                    asm::delay((MAX_ADVREGEN_STARTUP_US * 1_000_000) / clocks.sysclk().0);
                 }
 
                 /// busy ADC read
@@ -542,6 +545,43 @@ macro_rules! adc_hal {
     }
 }
 
+/// ADC Instance
+pub trait Instance:
+    Deref<Target = adc1::RegisterBlock> + crate::private::Sealed
+{
+    /// Shared Instance / Registerblock between multiple ADCs
+    type SharedInstance;
+    #[doc(hidden)]
+    fn enable_clock(ahb: &mut AHB, common: &mut Self::SharedInstance);
+    #[doc(hidden)]
+    fn clock(clocks: &Clocks) -> Hertz;
+}
+
+/// Shared ADC Register Block
+pub trait SharedInstance:
+    Deref<Target = adc1_2::RegisterBlock> + crate::private::Sealed
+{
+}
+
+
+
+// Macro to implement ADC functionallity for ADC1 and ADC2
+// TODO: Extend/differentiate beyond f303.
+impl Instance for ADC1 {
+    type SharedInstance = ADC1_2;
+    fn enable_clock(&self, ahb: &mut AHB, common: &mut Self::SharedInstance) {
+        ahb.enr().modify(|_, w| w.adc12en().enabled());
+        // TODO: Check how to handle adc commeon
+        adc_common.ccr.modify(|_, w| w
+            .ckmode().variant(self.clock_mode.into())
+        );
+    }
+
+    fn clock(clocks: &Clocks) -> Hertz {
+
+    }
+}
+
 // Macro to implement ADC functionallity for ADC1 and ADC2
 // TODO: Extend/differentiate beyond f303.
 macro_rules! adc12_hal {