@@ -222,7 +222,7 @@ macro_rules! hal {
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for byte in buffer {
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// Wait until we have received something
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busy_wait!( self . i2c, rxne, is_not_empty) ;
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-
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+
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* byte = self . i2c. rxdr. read( ) . rxdata( ) . bits( ) ;
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}
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@@ -246,47 +246,59 @@ macro_rules! hal {
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type Error = Error ;
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fn write( & mut self , addr: u8 , bytes: & [ u8 ] ) -> Result <( ) , Error > {
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- assert!( bytes. len( ) > 0 ) ;
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-
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// Detect Bus busy
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if self . i2c. isr. read( ) . busy( ) . is_busy( ) {
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return Err ( Error :: Busy ) ;
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}
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- let end = bytes. len( ) / 0xFF ;
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-
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- // Process 255 bytes at a time
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- for ( i, bytes) in bytes. chunks( 0xFF ) . enumerate( ) {
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- // Prepare to send `bytes`
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+ if bytes. len( ) == 0 {
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+ // 0 byte write
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self . i2c. cr2. modify( |_, w| {
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- if i == 0 {
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- w
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- . add10( ) . bit7( )
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- . sadd( ) . bits( ( addr << 1 ) as u16 )
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- . rd_wrn( ) . write( )
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- . start( ) . start( ) ;
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+ w
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+ . add10( ) . bit7( )
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+ . sadd( ) . bits( ( addr << 1 ) as u16 )
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+ . rd_wrn( ) . write( )
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+ . nbytes( ) . bits( 0 )
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+ . reload( ) . completed( )
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+ . autoend( ) . automatic( )
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+ . start( ) . start( )
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+ } ) ;
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+ } else {
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+ let end = bytes. len( ) / 0xFF ;
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+
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+ // Process 255 bytes at a time
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+ for ( i, bytes) in bytes. chunks( 0xFF ) . enumerate( ) {
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+ // Prepare to send `bytes`
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+ self . i2c. cr2. modify( |_, w| {
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+ if i == 0 {
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+ w
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+ . add10( ) . bit7( )
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+ . sadd( ) . bits( ( addr << 1 ) as u16 )
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+ . rd_wrn( ) . write( )
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+ . start( ) . start( ) ;
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+ }
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+ w. nbytes( ) . bits( bytes. len( ) as u8 ) ;
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+ if i != end {
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+ w. reload( ) . not_completed( )
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+ } else {
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+ w. reload( ) . completed( ) . autoend( ) . automatic( )
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+ }
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+ } ) ;
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+
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+ for byte in bytes {
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+ // Wait until we are allowed to send data
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+ // (START has been ACKed or last byte went through)
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+ busy_wait!( self . i2c, txis, is_empty) ;
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+
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+ // Put byte on the wire
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+ // NOTE(write): Writes all non-reserved bits.
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+ self . i2c. txdr. write( |w| w. txdata( ) . bits( * byte) ) ;
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}
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- w . nbytes ( ) . bits ( bytes . len ( ) as u8 ) ;
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+
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if i != end {
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- w. reload( ) . not_completed( )
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- } else {
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- w. reload( ) . completed( ) . autoend( ) . automatic( )
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+ // Wait until the last transmission is finished
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+ busy_wait!( self . i2c, tcr, is_complete) ;
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}
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- } ) ;
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-
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- for byte in bytes {
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- // Wait until we are allowed to send data
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- // (START has been ACKed or last byte went through)
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- busy_wait!( self . i2c, txis, is_empty) ;
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-
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- // Put byte on the wire
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- // NOTE(write): Writes all non-reserved bits.
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- self . i2c. txdr. write( |w| w. txdata( ) . bits( * byte) ) ;
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- }
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-
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- if i != end {
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- // Wait until the last transmission is finished
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- busy_wait!( self . i2c, tcr, is_complete) ;
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}
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}
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@@ -382,7 +394,7 @@ macro_rules! hal {
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for byte in buffer {
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// Wait until we have received something
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busy_wait!( self . i2c, rxne, is_not_empty) ;
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-
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+
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* byte = self . i2c. rxdr. read( ) . rxdata( ) . bits( ) ;
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}
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