Skip to content

Commit da62a18

Browse files
Sh3Rm4nSh3Rm4n
committed
Remove u32 from embedded-time calls
The extension trait is now only implemented for `u32`, so defining the type is not needed anymore and can be inferred.
1 parent 03d2011 commit da62a18

File tree

8 files changed

+84
-84
lines changed

8 files changed

+84
-84
lines changed

‎CHANGELOG.md

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -44,11 +44,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
4444
// The supplied frequencies must be in `MHz`.
4545
let clocks = rcc
4646
.cfgr
47-
.use_hse(8u32.MHz())
48-
.hclk(48u32.MHz())
49-
.sysclk(48u32.MHz())
50-
.pclk1(12u32.MHz())
51-
.pclk2(12u32.MHz())
47+
.use_hse(8.MHz())
48+
.hclk(48.MHz())
49+
.sysclk(48.MHz())
50+
.pclk1(12.MHz())
51+
.pclk2(12.MHz())
5252
```
5353

5454
- You always required to select a sub-target for target chips ([#216])

‎examples/can.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,10 @@ fn main() -> ! {
3131

3232
let _clocks = rcc
3333
.cfgr
34-
.use_hse(32u32.MHz())
35-
.sysclk(32u32.MHz())
36-
.pclk1(16u32.MHz())
37-
.pclk2(16u32.MHz())
34+
.use_hse(32.MHz())
35+
.sysclk(32.MHz())
36+
.pclk1(16.MHz())
37+
.pclk2(16.MHz())
3838
.freeze(&mut flash.acr);
3939

4040
// Configure CAN RX and TX pins (AF9)
@@ -58,13 +58,13 @@ fn main() -> ! {
5858
.into_push_pull_output(&mut gpiob.moder, &mut gpiob.otyper);
5959
led0.set_high().unwrap();
6060

61-
let filter = CanFilter::from_mask(0b100, ID as u32);
61+
let filter = CanFilter::from_mask(0b100, ID.into());
6262
rx0.set_filter(filter);
6363

6464
// Watchdog makes sure this gets restarted periodically if nothing happens
6565
let mut iwdg = IndependentWatchDog::new(dp.IWDG);
6666
iwdg.stop_on_debug(&dp.DBGMCU, true);
67-
iwdg.start(100u32.milliseconds());
67+
iwdg.start(100.milliseconds());
6868

6969
// Send an initial message!
7070
asm::delay(100_000);

‎examples/i2c_scanner.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ fn main() -> ! {
4141
let mut i2c = hal::i2c::I2c::new(
4242
dp.I2C1,
4343
(scl, sda),
44-
100u32.kHz().try_into().unwrap(),
44+
100.kHz().try_into().unwrap(),
4545
clocks,
4646
&mut rcc.apb1,
4747
);

‎examples/pwm.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ fn main() -> ! {
2828
// Configure our clocks
2929
let mut flash = dp.FLASH.constrain();
3030
let mut rcc = dp.RCC.constrain();
31-
let clocks = rcc.cfgr.sysclk(16u32.MHz()).freeze(&mut flash.acr);
31+
let clocks = rcc.cfgr.sysclk(16.MHz()).freeze(&mut flash.acr);
3232

3333
// Prep the pins we need in their correct alternate function
3434
let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);
@@ -72,9 +72,9 @@ fn main() -> ! {
7272
// A four channel general purpose timer that's broadly available
7373
let tim3_channels = tim3(
7474
dp.TIM3,
75-
1280, // resolution of duty cycle
76-
50u32.Hz(), // frequency of period
77-
&clocks, // To get the timer's clock speed
75+
1280, // resolution of duty cycle
76+
50.Hz(), // frequency of period
77+
&clocks, // To get the timer's clock speed
7878
);
7979

8080
// Channels without pins cannot be enabled, so we can't forget to
@@ -121,9 +121,9 @@ fn main() -> ! {
121121
// A 32-bit timer, so we can set a larger resolution
122122
let tim2_channels = tim2(
123123
dp.TIM2,
124-
160000, // resolution of duty cycle
125-
50u32.Hz(), // frequency of period
126-
&clocks, // To get the timer's clock speed
124+
160000, // resolution of duty cycle
125+
50.Hz(), // frequency of period
126+
&clocks, // To get the timer's clock speed
127127
);
128128

129129
let mut tim2_ch3 = tim2_channels.2.output_to_pb10(pb10);
@@ -136,9 +136,9 @@ fn main() -> ! {
136136
// just use it directly
137137
let mut tim16_ch1 = tim16(
138138
dp.TIM16,
139-
1280, // resolution of duty cycle
140-
50u32.Hz(), // frequency of period
141-
&clocks, // To get the timer's clock speed
139+
1280, // resolution of duty cycle
140+
50.Hz(), // frequency of period
141+
&clocks, // To get the timer's clock speed
142142
)
143143
.output_to_pb8(pb8);
144144
tim16_ch1.set_duty(tim16_ch1.get_max_duty() / 20); // 5% duty cyle

‎examples/spi.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@ fn main() -> ! {
2626

2727
let clocks = rcc
2828
.cfgr
29-
.use_hse(8u32.MHz())
30-
.sysclk(48u32.MHz())
31-
.pclk1(24u32.MHz())
29+
.use_hse(8.MHz())
30+
.sysclk(48.MHz())
31+
.pclk1(24.MHz())
3232
.freeze(&mut flash.acr);
3333

3434
// Configure pins for SPI

‎examples/usb_serial.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,10 @@ fn main() -> ! {
2626

2727
let clocks = rcc
2828
.cfgr
29-
.use_hse(8u32.MHz())
30-
.sysclk(48u32.MHz())
31-
.pclk1(24u32.MHz())
32-
.pclk2(24u32.MHz())
29+
.use_hse(8.MHz())
30+
.sysclk(48.MHz())
31+
.pclk1(24.MHz())
32+
.pclk2(24.MHz())
3333
.freeze(&mut flash.acr);
3434

3535
assert!(clocks.usbclk_valid());

‎testsuite/tests/rcc.rs

Lines changed: 54 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -18,10 +18,10 @@ mod tests {
1818

1919
let clock = rcc.cfgr.freeze(&mut flash.acr);
2020

21-
defmt::assert!(clock.sysclk() == 8u32.MHz());
22-
defmt::assert!(clock.hclk() == 8u32.MHz());
23-
defmt::assert!(clock.pclk2() == 8u32.MHz());
24-
defmt::assert!(clock.pclk1() == 8u32.MHz());
21+
defmt::assert!(clock.sysclk() == 8.MHz());
22+
defmt::assert!(clock.hclk() == 8.MHz());
23+
defmt::assert!(clock.pclk2() == 8.MHz());
24+
defmt::assert!(clock.pclk1() == 8.MHz());
2525
defmt::assert!(!clock.usbclk_valid());
2626
}
2727

@@ -37,14 +37,14 @@ mod tests {
3737

3838
let clock = rcc
3939
.cfgr
40-
.use_hse(8u32.MHz())
41-
.sysclk(15u32.MHz())
40+
.use_hse(8.MHz())
41+
.sysclk(15.MHz())
4242
.freeze(&mut flash.acr);
4343

44-
defmt::assert!(clock.sysclk() == 15u32.MHz());
45-
defmt::assert!(clock.hclk() == 15u32.MHz());
46-
defmt::assert!(clock.pclk2() == 15u32.MHz());
47-
defmt::assert!(clock.pclk1() == 15u32.MHz());
44+
defmt::assert!(clock.sysclk() == 15.MHz());
45+
defmt::assert!(clock.hclk() == 15.MHz());
46+
defmt::assert!(clock.pclk2() == 15.MHz());
47+
defmt::assert!(clock.pclk1() == 15.MHz());
4848
defmt::assert!(!clock.usbclk_valid());
4949
}
5050

@@ -64,12 +64,12 @@ mod tests {
6464
feature = "stm32f303xe",
6565
feature = "stm32f398",
6666
))] {
67-
let clock = rcc.cfgr.sysclk(72u32.MHz()).freeze(&mut flash.acr);
67+
let clock = rcc.cfgr.sysclk(72.MHz()).freeze(&mut flash.acr);
6868

69-
defmt::assert!(clock.sysclk() == 72u32.MHz());
70-
defmt::assert!(clock.hclk() == 72u32.MHz());
71-
defmt::assert!(clock.pclk2() == 72u32.MHz());
72-
defmt::assert!(clock.pclk1() == 36u32.MHz());
69+
defmt::assert!(clock.sysclk() == 72.MHz());
70+
defmt::assert!(clock.hclk() == 72.MHz());
71+
defmt::assert!(clock.pclk2() == 72.MHz());
72+
defmt::assert!(clock.pclk1() == 36.MHz());
7373
} else {
7474
// Notice the strange part about 67 being reduced to 64?
7575
//
@@ -78,12 +78,12 @@ mod tests {
7878
// and the resolution is therefor lower.
7979
// Because of the implementation the clock is then approximated to
8080
// the highest possible value (64 Mhz).
81-
let clock = rcc.cfgr.sysclk(67u32.MHz()).freeze(&mut flash.acr);
81+
let clock = rcc.cfgr.sysclk(67.MHz()).freeze(&mut flash.acr);
8282

83-
defmt::assert!(clock.sysclk() == 64u32.MHz());
84-
defmt::assert!(clock.hclk() == 64u32.MHz());
85-
defmt::assert!(clock.pclk2() == 64u32.MHz());
86-
defmt::assert!(clock.pclk1() == 32u32.MHz());
83+
defmt::assert!(clock.sysclk() == 64.MHz());
84+
defmt::assert!(clock.hclk() == 64.MHz());
85+
defmt::assert!(clock.pclk2() == 64.MHz());
86+
defmt::assert!(clock.pclk1() == 32.MHz());
8787
}
8888
}
8989

@@ -100,14 +100,14 @@ mod tests {
100100

101101
let clock = rcc
102102
.cfgr
103-
.use_hse(8u32.MHz())
104-
.sysclk(32u32.MHz())
103+
.use_hse(8.MHz())
104+
.sysclk(32.MHz())
105105
.freeze(&mut flash.acr);
106106

107-
defmt::assert!(clock.sysclk() == 32u32.MHz());
108-
defmt::assert!(clock.hclk() == 32u32.MHz());
109-
defmt::assert!(clock.pclk2() == 32u32.MHz());
110-
defmt::assert!(clock.pclk1() == 32u32.MHz());
107+
defmt::assert!(clock.sysclk() == 32.MHz());
108+
defmt::assert!(clock.hclk() == 32.MHz());
109+
defmt::assert!(clock.pclk2() == 32.MHz());
110+
defmt::assert!(clock.pclk1() == 32.MHz());
111111
defmt::assert!(!clock.usbclk_valid());
112112
}
113113

@@ -122,14 +122,14 @@ mod tests {
122122

123123
let clock = rcc
124124
.cfgr
125-
.use_hse(8u32.MHz())
126-
.sysclk(48u32.MHz())
125+
.use_hse(8.MHz())
126+
.sysclk(48.MHz())
127127
.freeze(&mut flash.acr); // works
128128

129-
defmt::assert!(clock.sysclk() == 48u32.MHz());
130-
defmt::assert!(clock.hclk() == 48u32.MHz());
131-
defmt::assert!(clock.pclk2() == 48u32.MHz());
132-
defmt::assert!(clock.pclk1() == 24u32.MHz());
129+
defmt::assert!(clock.sysclk() == 48.MHz());
130+
defmt::assert!(clock.hclk() == 48.MHz());
131+
defmt::assert!(clock.pclk2() == 48.MHz());
132+
defmt::assert!(clock.pclk1() == 24.MHz());
133133
defmt::assert!(clock.usbclk_valid());
134134
}
135135

@@ -142,17 +142,17 @@ mod tests {
142142

143143
let clock = rcc
144144
.cfgr
145-
.use_hse(8u32.MHz())
146-
.hclk(48u32.MHz())
147-
.sysclk(48u32.MHz())
148-
.pclk1(12u32.MHz())
149-
.pclk2(12u32.MHz())
145+
.use_hse(8.MHz())
146+
.hclk(48.MHz())
147+
.sysclk(48.MHz())
148+
.pclk1(12.MHz())
149+
.pclk2(12.MHz())
150150
.freeze(&mut flash.acr);
151151

152-
defmt::assert!(clock.sysclk() == 48u32.MHz());
153-
defmt::assert!(clock.hclk() == 48u32.MHz());
154-
defmt::assert!(clock.pclk2() == 12u32.MHz());
155-
defmt::assert!(clock.pclk1() == 12u32.MHz());
152+
defmt::assert!(clock.sysclk() == 48.MHz());
153+
defmt::assert!(clock.hclk() == 48.MHz());
154+
defmt::assert!(clock.pclk2() == 12.MHz());
155+
defmt::assert!(clock.pclk1() == 12.MHz());
156156
defmt::assert!(clock.usbclk_valid());
157157
}
158158

@@ -166,15 +166,15 @@ mod tests {
166166

167167
let clock = rcc
168168
.cfgr
169-
.use_hse(8u32.MHz())
170-
.pclk1(16u32.MHz())
171-
.sysclk(64u32.MHz())
169+
.use_hse(8.MHz())
170+
.pclk1(16.MHz())
171+
.sysclk(64.MHz())
172172
.freeze(&mut flash.acr);
173173

174-
defmt::assert!(clock.sysclk() == 64u32.MHz());
175-
defmt::assert!(clock.hclk() == 64u32.MHz());
176-
defmt::assert!(clock.pclk2() == 64u32.MHz());
177-
defmt::assert!(clock.pclk1() == 16u32.MHz());
174+
defmt::assert!(clock.sysclk() == 64.MHz());
175+
defmt::assert!(clock.hclk() == 64.MHz());
176+
defmt::assert!(clock.pclk2() == 64.MHz());
177+
defmt::assert!(clock.pclk1() == 16.MHz());
178178
defmt::assert!(!clock.usbclk_valid());
179179
}
180180

@@ -189,14 +189,14 @@ mod tests {
189189

190190
let clock = rcc
191191
.cfgr
192-
.use_hse(8u32.MHz())
193-
.sysclk(72u32.MHz())
192+
.use_hse(8.MHz())
193+
.sysclk(72.MHz())
194194
.freeze(&mut flash.acr);
195195

196-
defmt::assert!(clock.sysclk() == 72u32.MHz());
197-
defmt::assert!(clock.hclk() == 72u32.MHz());
198-
defmt::assert!(clock.pclk2() == 72u32.MHz());
199-
defmt::assert!(clock.pclk1() == 36u32.MHz());
196+
defmt::assert!(clock.sysclk() == 72.MHz());
197+
defmt::assert!(clock.hclk() == 72.MHz());
198+
defmt::assert!(clock.pclk2() == 72.MHz());
199+
defmt::assert!(clock.pclk1() == 36.MHz());
200200
defmt::assert!(clock.usbclk_valid());
201201
}
202202
}

‎testsuite/tests/watchdog.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ mod tests {
6161
// the probe-run output is repeated many times (as the core is restareted).
6262
fn feed(state: &mut State) {
6363
// Calculate some overhead which is introduced by asm::delay
64-
let interval_wo_overhead = INTERVAL - 35u32.milliseconds();
64+
let interval_wo_overhead = INTERVAL - 35.milliseconds();
6565
let delay: u32 = (u32::try_from(
6666
Nanoseconds::from(interval_wo_overhead).integer()
6767
/ u64::from(

0 commit comments

Comments
 (0)