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Update to new pac
1 parent b0cead1 commit dcd1f25

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17 files changed

+784
-736
lines changed

17 files changed

+784
-736
lines changed

‎Cargo.toml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@ num-traits = { version = "0.2.17", default-features = false}
4242
paste = "1.0.14"
4343
rtcc = { version = "0.3.0", optional = true }
4444
stm32-usbd = { version = "0.6.0", optional = true }
45-
stm32f3 = { version = "0.15.1", default-features = false }
45+
#stm32f3 = { version = "0.15.1", default-features = false }
46+
stm32f3 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies", default-features = false }
4647
void = { version = "1.0.2", default-features = false }
4748

4849
[dev-dependencies]

‎src/adc.rs

Lines changed: 212 additions & 208 deletions
Large diffs are not rendered by default.

‎src/adc/config.rs

Lines changed: 90 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
//! adc::set_align(config::Align::Right);
3030
//! ```
3131
32-
use crate::pac::adc1::{cfgr, smpr1::SMP1_A, smpr2::SMP10_A};
32+
use crate::pac::adc1::{cfgr, smpr1::SMP1, smpr2::SMP10};
3333
use core::convert::TryFrom;
3434

3535
/// The place in the sequence a given channel should be captured.
@@ -166,24 +166,24 @@ pub enum Resolution {
166166
Six,
167167
}
168168

169-
impl From<Resolution> for cfgr::RES_A {
169+
impl From<Resolution> for cfgr::RES {
170170
fn from(r: Resolution) -> Self {
171171
match r {
172-
Resolution::Twelve => cfgr::RES_A::Bits12,
173-
Resolution::Ten => cfgr::RES_A::Bits10,
174-
Resolution::Eight => cfgr::RES_A::Bits8,
175-
Resolution::Six => cfgr::RES_A::Bits6,
172+
Resolution::Twelve => cfgr::RES::Bits12,
173+
Resolution::Ten => cfgr::RES::Bits10,
174+
Resolution::Eight => cfgr::RES::Bits8,
175+
Resolution::Six => cfgr::RES::Bits6,
176176
}
177177
}
178178
}
179179

180-
impl From<cfgr::RES_A> for Resolution {
181-
fn from(r: cfgr::RES_A) -> Self {
180+
impl From<cfgr::RES> for Resolution {
181+
fn from(r: cfgr::RES) -> Self {
182182
match r {
183-
cfgr::RES_A::Bits12 => Resolution::Twelve,
184-
cfgr::RES_A::Bits10 => Resolution::Ten,
185-
cfgr::RES_A::Bits8 => Resolution::Eight,
186-
cfgr::RES_A::Bits6 => Resolution::Six,
183+
cfgr::RES::Bits12 => Resolution::Twelve,
184+
cfgr::RES::Bits10 => Resolution::Ten,
185+
cfgr::RES::Bits8 => Resolution::Eight,
186+
cfgr::RES::Bits6 => Resolution::Six,
187187
}
188188
}
189189
}
@@ -239,28 +239,28 @@ pub enum ExternalTrigger {
239239
Tim3Cc4(TriggerMode),
240240
}
241241

242-
impl From<ExternalTrigger> for cfgr::EXTSEL_A {
242+
impl From<ExternalTrigger> for cfgr::EXTSEL {
243243
fn from(et: ExternalTrigger) -> Self {
244244
match et {
245-
ExternalTrigger::Tim1Cc1(_) => cfgr::EXTSEL_A::Tim1Cc1,
246-
ExternalTrigger::Tim1Cc2(_) => cfgr::EXTSEL_A::Tim1Cc2,
247-
ExternalTrigger::Tim1Cc3(_) => cfgr::EXTSEL_A::Tim1Cc3,
248-
ExternalTrigger::Tim2Cc2(_) => cfgr::EXTSEL_A::Tim2Cc2,
249-
ExternalTrigger::Tim3Trgo(_) => cfgr::EXTSEL_A::Tim3Trgo,
250-
ExternalTrigger::Exti11(_) => cfgr::EXTSEL_A::Exti11,
251-
ExternalTrigger::HrtimAdcTrg1(_) => cfgr::EXTSEL_A::HrtimAdctrg1,
252-
ExternalTrigger::HrtimAdcTrg3(_) => cfgr::EXTSEL_A::HrtimAdctrg3,
253-
ExternalTrigger::Tim1Trgo(_) => cfgr::EXTSEL_A::Tim1Trgo,
254-
ExternalTrigger::Tim1Trgo2(_) => cfgr::EXTSEL_A::Tim1Trgo2,
255-
ExternalTrigger::Tim2Trgo(_) => cfgr::EXTSEL_A::Tim2Trgo,
256-
ExternalTrigger::Tim6Trgo(_) => cfgr::EXTSEL_A::Tim6Trgo,
257-
ExternalTrigger::Tim15Trgo(_) => cfgr::EXTSEL_A::Tim15Trgo,
258-
ExternalTrigger::Tim3Cc4(_) => cfgr::EXTSEL_A::Tim3Cc4,
245+
ExternalTrigger::Tim1Cc1(_) => cfgr::EXTSEL::Tim1Cc1,
246+
ExternalTrigger::Tim1Cc2(_) => cfgr::EXTSEL::Tim1Cc2,
247+
ExternalTrigger::Tim1Cc3(_) => cfgr::EXTSEL::Tim1Cc3,
248+
ExternalTrigger::Tim2Cc2(_) => cfgr::EXTSEL::Tim2Cc2,
249+
ExternalTrigger::Tim3Trgo(_) => cfgr::EXTSEL::Tim3Trgo,
250+
ExternalTrigger::Exti11(_) => cfgr::EXTSEL::Exti11,
251+
ExternalTrigger::HrtimAdcTrg1(_) => cfgr::EXTSEL::HrtimAdctrg1,
252+
ExternalTrigger::HrtimAdcTrg3(_) => cfgr::EXTSEL::HrtimAdctrg3,
253+
ExternalTrigger::Tim1Trgo(_) => cfgr::EXTSEL::Tim1Trgo,
254+
ExternalTrigger::Tim1Trgo2(_) => cfgr::EXTSEL::Tim1Trgo2,
255+
ExternalTrigger::Tim2Trgo(_) => cfgr::EXTSEL::Tim2Trgo,
256+
ExternalTrigger::Tim6Trgo(_) => cfgr::EXTSEL::Tim6Trgo,
257+
ExternalTrigger::Tim15Trgo(_) => cfgr::EXTSEL::Tim15Trgo,
258+
ExternalTrigger::Tim3Cc4(_) => cfgr::EXTSEL::Tim3Cc4,
259259
}
260260
}
261261
}
262262

263-
impl From<ExternalTrigger> for cfgr::EXTEN_A {
263+
impl From<ExternalTrigger> for cfgr::EXTEN {
264264
fn from(et: ExternalTrigger) -> Self {
265265
match et {
266266
ExternalTrigger::Tim1Cc1(n)
@@ -301,12 +301,12 @@ pub enum TriggerMode {
301301
BothEdges,
302302
}
303303

304-
impl From<TriggerMode> for cfgr::EXTEN_A {
304+
impl From<TriggerMode> for cfgr::EXTEN {
305305
fn from(tm: TriggerMode) -> Self {
306306
match tm {
307-
TriggerMode::RisingEdge => cfgr::EXTEN_A::RisingEdge,
308-
TriggerMode::FallingEdge => cfgr::EXTEN_A::FallingEdge,
309-
TriggerMode::BothEdges => cfgr::EXTEN_A::BothEdges,
307+
TriggerMode::RisingEdge => cfgr::EXTEN::RisingEdge,
308+
TriggerMode::FallingEdge => cfgr::EXTEN::FallingEdge,
309+
TriggerMode::BothEdges => cfgr::EXTEN::BothEdges,
310310
}
311311
}
312312
}
@@ -335,20 +335,20 @@ pub enum DataAlignment {
335335
Left,
336336
}
337337

338-
impl From<DataAlignment> for cfgr::ALIGN_A {
338+
impl From<DataAlignment> for cfgr::ALIGN {
339339
fn from(a: DataAlignment) -> Self {
340340
match a {
341-
DataAlignment::Right => cfgr::ALIGN_A::Right,
342-
DataAlignment::Left => cfgr::ALIGN_A::Left,
341+
DataAlignment::Right => cfgr::ALIGN::Right,
342+
DataAlignment::Left => cfgr::ALIGN::Left,
343343
}
344344
}
345345
}
346346

347-
impl From<cfgr::ALIGN_A> for DataAlignment {
348-
fn from(a: cfgr::ALIGN_A) -> Self {
347+
impl From<cfgr::ALIGN> for DataAlignment {
348+
fn from(a: cfgr::ALIGN) -> Self {
349349
match a {
350-
cfgr::ALIGN_A::Right => DataAlignment::Right,
351-
cfgr::ALIGN_A::Left => DataAlignment::Left,
350+
cfgr::ALIGN::Right => DataAlignment::Right,
351+
cfgr::ALIGN::Left => DataAlignment::Left,
352352
}
353353
}
354354
}
@@ -435,20 +435,20 @@ pub enum OverrunMode {
435435
Overwrite,
436436
}
437437

438-
impl From<cfgr::OVRMOD_A> for OverrunMode {
439-
fn from(a: cfgr::OVRMOD_A) -> Self {
438+
impl From<cfgr::OVRMOD> for OverrunMode {
439+
fn from(a: cfgr::OVRMOD) -> Self {
440440
match a {
441-
cfgr::OVRMOD_A::Preserve => OverrunMode::Preserve,
442-
cfgr::OVRMOD_A::Overwrite => OverrunMode::Overwrite,
441+
cfgr::OVRMOD::Preserve => OverrunMode::Preserve,
442+
cfgr::OVRMOD::Overwrite => OverrunMode::Overwrite,
443443
}
444444
}
445445
}
446446

447-
impl From<OverrunMode> for cfgr::OVRMOD_A {
447+
impl From<OverrunMode> for cfgr::OVRMOD {
448448
fn from(a: OverrunMode) -> Self {
449449
match a {
450-
OverrunMode::Preserve => cfgr::OVRMOD_A::Preserve,
451-
OverrunMode::Overwrite => cfgr::OVRMOD_A::Overwrite,
450+
OverrunMode::Preserve => cfgr::OVRMOD::Preserve,
451+
OverrunMode::Overwrite => cfgr::OVRMOD::Overwrite,
452452
}
453453
}
454454
}
@@ -542,62 +542,62 @@ impl From<SampleTime> for f32 {
542542
}
543543
}
544544

545-
impl From<SampleTime> for SMP1_A {
545+
impl From<SampleTime> for SMP1 {
546546
fn from(t: SampleTime) -> Self {
547547
match t {
548-
SampleTime::Cycles1C5 => Self::Cycles15,
549-
SampleTime::Cycles2C5 => Self::Cycles25,
550-
SampleTime::Cycles4C5 => Self::Cycles45,
551-
SampleTime::Cycles7C5 => Self::Cycles75,
552-
SampleTime::Cycles19C5 => Self::Cycles195,
553-
SampleTime::Cycles61C5 => Self::Cycles615,
554-
SampleTime::Cycles181C5 => Self::Cycles1815,
555-
SampleTime::Cycles601C5 => Self::Cycles6015,
548+
SampleTime::Cycles1C5 => Self::Cycles1_5,
549+
SampleTime::Cycles2C5 => Self::Cycles2_5,
550+
SampleTime::Cycles4C5 => Self::Cycles4_5,
551+
SampleTime::Cycles7C5 => Self::Cycles7_5,
552+
SampleTime::Cycles19C5 => Self::Cycles19_5,
553+
SampleTime::Cycles61C5 => Self::Cycles61_5,
554+
SampleTime::Cycles181C5 => Self::Cycles181_5,
555+
SampleTime::Cycles601C5 => Self::Cycles601_5,
556556
}
557557
}
558558
}
559559

560-
impl From<SampleTime> for SMP10_A {
560+
impl From<SampleTime> for SMP10 {
561561
fn from(t: SampleTime) -> Self {
562562
match t {
563-
SampleTime::Cycles1C5 => Self::Cycles15,
564-
SampleTime::Cycles2C5 => Self::Cycles25,
565-
SampleTime::Cycles4C5 => Self::Cycles45,
566-
SampleTime::Cycles7C5 => Self::Cycles75,
567-
SampleTime::Cycles19C5 => Self::Cycles195,
568-
SampleTime::Cycles61C5 => Self::Cycles615,
569-
SampleTime::Cycles181C5 => Self::Cycles1815,
570-
SampleTime::Cycles601C5 => Self::Cycles6015,
563+
SampleTime::Cycles1C5 => Self::Cycles1_5,
564+
SampleTime::Cycles2C5 => Self::Cycles2_5,
565+
SampleTime::Cycles4C5 => Self::Cycles4_5,
566+
SampleTime::Cycles7C5 => Self::Cycles7_5,
567+
SampleTime::Cycles19C5 => Self::Cycles19_5,
568+
SampleTime::Cycles61C5 => Self::Cycles61_5,
569+
SampleTime::Cycles181C5 => Self::Cycles181_5,
570+
SampleTime::Cycles601C5 => Self::Cycles601_5,
571571
}
572572
}
573573
}
574574

575-
impl From<SMP1_A> for SampleTime {
576-
fn from(t: SMP1_A) -> Self {
575+
impl From<SMP1> for SampleTime {
576+
fn from(t: SMP1) -> Self {
577577
match t {
578-
SMP1_A::Cycles15 => Self::Cycles1C5,
579-
SMP1_A::Cycles25 => Self::Cycles2C5,
580-
SMP1_A::Cycles45 => Self::Cycles4C5,
581-
SMP1_A::Cycles75 => Self::Cycles7C5,
582-
SMP1_A::Cycles195 => Self::Cycles19C5,
583-
SMP1_A::Cycles615 => Self::Cycles61C5,
584-
SMP1_A::Cycles1815 => Self::Cycles181C5,
585-
SMP1_A::Cycles6015 => Self::Cycles601C5,
578+
SMP1::Cycles1_5 => Self::Cycles1C5,
579+
SMP1::Cycles2_5 => Self::Cycles2C5,
580+
SMP1::Cycles4_5 => Self::Cycles4C5,
581+
SMP1::Cycles7_5 => Self::Cycles7C5,
582+
SMP1::Cycles19_5 => Self::Cycles19C5,
583+
SMP1::Cycles61_5 => Self::Cycles61C5,
584+
SMP1::Cycles181_5 => Self::Cycles181C5,
585+
SMP1::Cycles601_5 => Self::Cycles601C5,
586586
}
587587
}
588588
}
589589

590-
impl From<SMP10_A> for SampleTime {
591-
fn from(t: SMP10_A) -> Self {
590+
impl From<SMP10> for SampleTime {
591+
fn from(t: SMP10) -> Self {
592592
match t {
593-
SMP10_A::Cycles15 => Self::Cycles1C5,
594-
SMP10_A::Cycles25 => Self::Cycles2C5,
595-
SMP10_A::Cycles45 => Self::Cycles4C5,
596-
SMP10_A::Cycles75 => Self::Cycles7C5,
597-
SMP10_A::Cycles195 => Self::Cycles19C5,
598-
SMP10_A::Cycles615 => Self::Cycles61C5,
599-
SMP10_A::Cycles1815 => Self::Cycles181C5,
600-
SMP10_A::Cycles6015 => Self::Cycles601C5,
593+
SMP10::Cycles1_5 => Self::Cycles1C5,
594+
SMP10::Cycles2_5 => Self::Cycles2C5,
595+
SMP10::Cycles4_5 => Self::Cycles4C5,
596+
SMP10::Cycles7_5 => Self::Cycles7C5,
597+
SMP10::Cycles19_5 => Self::Cycles19C5,
598+
SMP10::Cycles61_5 => Self::Cycles61C5,
599+
SMP10::Cycles181_5 => Self::Cycles181C5,
600+
SMP10::Cycles601_5 => Self::Cycles601C5,
601601
}
602602
}
603603
}
@@ -776,7 +776,7 @@ pub enum ConversionMode {
776776
// Scan,
777777
}
778778

779-
impl From<ConversionMode> for cfgr::CONT_A {
779+
impl From<ConversionMode> for cfgr::CONT {
780780
fn from(mode: ConversionMode) -> Self {
781781
match mode {
782782
ConversionMode::Single | ConversionMode::Discontinuous(_) => Self::Single,
@@ -785,7 +785,7 @@ impl From<ConversionMode> for cfgr::CONT_A {
785785
}
786786
}
787787

788-
impl From<ConversionMode> for cfgr::DISCEN_A {
788+
impl From<ConversionMode> for cfgr::DISCEN {
789789
fn from(mode: ConversionMode) -> Self {
790790
match mode {
791791
ConversionMode::Single | ConversionMode::Continuous => Self::Disabled,
@@ -794,11 +794,11 @@ impl From<ConversionMode> for cfgr::DISCEN_A {
794794
}
795795
}
796796

797-
impl From<cfgr::CONT_A> for ConversionMode {
798-
fn from(mode: cfgr::CONT_A) -> Self {
797+
impl From<cfgr::CONT> for ConversionMode {
798+
fn from(mode: cfgr::CONT) -> Self {
799799
match mode {
800-
cfgr::CONT_A::Single => ConversionMode::Single,
801-
cfgr::CONT_A::Continuous => ConversionMode::Continuous,
800+
cfgr::CONT::Single => ConversionMode::Single,
801+
cfgr::CONT::Continuous => ConversionMode::Continuous,
802802
}
803803
}
804804
}

‎src/dac.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ impl Dac {
1818
DAC1::reset(apb1);
1919

2020
// Enable channel 1.
21-
regs.cr.modify(|_, w| w.en1().set_bit());
21+
regs.cr().modify(|_, w| w.en1().set_bit());
2222

2323
Self { regs }
2424
}
@@ -27,7 +27,7 @@ impl Dac {
2727
///
2828
/// Only the low 12 bits of `data` will be used, the rest is ignored.
2929
pub fn write_data(&mut self, data: u16) {
30-
self.regs.dhr12r1.write(|w| {
30+
self.regs.dhr12r1().write(|w| {
3131
#[allow(unused_unsafe)]
3232
// SAFETY: Direct write to register for easier sharing between different stm32f3xx svd
3333
// generated API

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