Simplify watchdog interval calculation

In addition to the changes, test them

Author: Sh3Rm4n

src/watchdog.rs

@@ -6,20 +6,37 @@
 //!
 //! [examples/can.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.6.1/examples/can.rs
 
+use embedded_time::fixed_point::FixedPoint;
+
 use crate::hal::watchdog::{Watchdog, WatchdogEnable};
 
-use crate::pac::{DBGMCU, IWDG};
-use crate::time::duration::*;
+use crate::pac::{iwdg::pr::PR_A, DBGMCU, IWDG};
+use crate::time::duration::Milliseconds;
+use crate::time::rate::Kilohertz;
 
-const LSI_KHZ: u32 = 40;
-const MAX_PR: u8 = 8;
-const MAX_RL: u16 = 0x1000;
+/// Frequency of the watchdog peripheral clock
+const LSI: Kilohertz = Kilohertz(40);
+// const MAX_PRESCALER: u8 = 0b0111;
+const MAX_PRESCALER: PR_A = PR_A::DIVIDEBY256;
+const MAX_RELOAD: u32 = 0x0FFF;
 
 /// Independent Watchdog Peripheral
 pub struct IndependentWatchDog {
     iwdg: IWDG,
 }
 
+fn into_division_value(psc: PR_A) -> u32 {
+    match psc {
+        PR_A::DIVIDEBY4 => 4,
+        PR_A::DIVIDEBY8 => 8,
+        PR_A::DIVIDEBY16 => 16,
+        PR_A::DIVIDEBY32 => 32,
+        PR_A::DIVIDEBY64 => 64,
+        PR_A::DIVIDEBY128 => 128,
+        PR_A::DIVIDEBY256 | PR_A::DIVIDEBY256BIS => 256,
+    }
+}
+
 impl IndependentWatchDog {
     /// Creates a new [`IndependentWatchDog`] without starting it.
     ///
@@ -35,52 +52,53 @@ impl IndependentWatchDog {
         dbg.apb1_fz.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
     }
 
-    fn setup(&self, timeout_ms: u32) {
-        let mut pr = 0;
-        while pr < MAX_PR && Self::timeout_period(pr, MAX_RL) < timeout_ms {
-            pr += 1;
+    /// Find and setup the next best prescaler and reload value for the selected timeout
+    fn setup(&self, timeout: Milliseconds) {
+        let mut reload: u32 =
+            timeout.integer() * LSI.integer() / into_division_value(PR_A::DIVIDEBY4);
+
+        // Reload is potentially to high to be stored in the register.
+        // The goal of this loop is to find the maximum possible reload value,
+        // which can be stored in the register, while still guaranteeing the wanted timeout.
+        //
+        // This is achived by increasing the prescaler value.
+        let mut psc = 0;
+        loop {
+            if psc >= MAX_PRESCALER as u8 {
+                // ceil the value to the maximum allow reload value
+                if reload > MAX_RELOAD {
+                    reload = MAX_RELOAD;
+                }
+                break;
+            }
+            if reload <= MAX_RELOAD {
+                break;
+            }
+            psc += 1;
+            // When the precaler value incresed, the reload value has to be halfed
+            // so that the timeout stays the same.
+            reload /= 2;
         }
 
-        let max_period = Self::timeout_period(pr, MAX_RL);
-        let max_rl = u32::from(MAX_RL);
-        let rl = (timeout_ms * max_rl / max_period).min(max_rl) as u16;
-
         self.access_registers(|iwdg| {
-            iwdg.pr.modify(|_, w| w.pr().bits(pr));
-            iwdg.rlr.modify(|_, w| w.rl().bits(rl));
+            iwdg.pr.modify(|_, w| w.pr().bits(psc));
+            iwdg.rlr.modify(|_, w| w.rl().bits(reload as u16));
         });
-    }
 
-    fn is_pr_updating(&self) -> bool {
-        self.iwdg.sr.read().pvu().bit()
+        // NOTE: As the watchdog can not be stopped once started,
+        // a free method is not provided.
+        // pub fn free(self) -> IWDG {}
     }
 
-    /// Returns the interval in ms
+    /// Returns the currently set interval
     pub fn interval(&self) -> Milliseconds {
-        while self.is_pr_updating() {}
+        // If the prescaler was changed wait until the change procedure is finished.
+        while self.iwdg.sr.read().pvu().bit() {}
 
-        let pr = self.iwdg.pr.read().pr().bits();
-        let rl = self.iwdg.rlr.read().rl().bits();
-        let ms = Self::timeout_period(pr, rl);
-        Milliseconds(ms)
-    }
+        let psc = self.iwdg.pr.read().pr().variant();
+        let reload = self.iwdg.rlr.read().rl().bits();
 
-    /// pr: Prescaler divider bits, rl: reload value
-    ///
-    /// Returns ms
-    fn timeout_period(pr: u8, rl: u16) -> u32 {
-        let divider: u32 = match pr {
-            0b000 => 4,
-            0b001 => 8,
-            0b010 => 16,
-            0b011 => 32,
-            0b100 => 64,
-            0b101 => 128,
-            0b110 => 256,
-            0b111 => 256,
-            _ => crate::panic!("Invalid IWDG prescaler divider"),
-        };
-        (u32::from(rl) + 1) * divider / LSI_KHZ
+        Milliseconds((into_division_value(psc) * u32::from(reload)) / LSI.integer())
     }
 
     fn access_registers<A, F: FnMut(&IWDG) -> A>(&self, mut f: F) -> A {
@@ -92,29 +110,13 @@ impl IndependentWatchDog {
         self.iwdg.kr.write(|w| w.key().reset());
         a
     }
-
-    /// Stop the watchdog timer
-    pub fn stop(&mut self) -> Self {
-        self.access_registers(|iwdg| {
-            iwdg.pr.reset();
-            iwdg.rlr.reset();
-        });
-    }
-
-    /// Release the independent watchdog peripheral.
-    ///
-    /// Disables the watchdog before releasing it.
-    pub fn free(mut self) -> IWDG {
-        self.stop();
-        self.iwdg
-    }
 }
 
 impl WatchdogEnable for IndependentWatchDog {
     type Time = Milliseconds;
 
     fn start<T: Into<Self::Time>>(&mut self, period: T) {
-        self.setup(period.into().integer());
+        self.setup(period.into());
 
         self.iwdg.kr.write(|w| w.key().start());
     }

testsuite/tests/watchdog.rs

@@ -22,20 +22,18 @@ struct State {
 #[defmt_test::tests]
 mod tests {
     use super::*;
-    use defmt::{assert_eq, unwrap};
-    use hal::time::duration::*; // imports all duration-related types and traits
-    use hal::time::duration::{Duration, Milliseconds, Nanoseconds, Seconds};
-    use hal::time::rate::Rate;
-    use hal::time::rate::*; // imports all rate-related types and traits
-    use hal::time::TimeInt;
+    use defmt::{assert, assert_eq, unwrap};
+    use hal::time::duration::{Milliseconds, Nanoseconds};
+    use hal::time::fixed_point::FixedPoint;
+    use hal::time::rate::{Kilohertz, Rate};
 
     const INTERVAL: Milliseconds = Milliseconds(100u32);
 
     #[init]
     fn init() -> State {
         let dp = unwrap!(hal::pac::Peripherals::take());
 
-        let mut rcc = dp.RCC.constrain();
+        let rcc = dp.RCC.constrain();
         let mut flash = dp.FLASH.constrain();
 
         // Watchdog makes sure this gets restarted periodically if nothing happens
@@ -62,7 +60,7 @@ mod tests {
     fn feed(state: &mut State) {
         // Calculate some overhead which is introduced by asm::delay
         let interval_wo_overhead = INTERVAL - 35.milliseconds();
-        let delay: u32 = (u32::try_from(
+        let delay: u32 = u32::try_from(
             Nanoseconds::from(interval_wo_overhead).integer()
                 / u64::from(
                     state
@@ -73,7 +71,7 @@ mod tests {
                         .integer(),
                 ),
         )
-        .unwrap());
+        .unwrap();
         defmt::info!("Delay = {}", delay);
         for _ in 0..5 {
             state.iwdg.feed();
@@ -82,10 +80,38 @@ mod tests {
         }
     }
 
+    // TODO:
+    #[test]
+    fn test_intervals_around_maximum(state: &mut State) {
+        const MAX_RELOAD: u32 = 0x0FFF;
+        const MAX_PRESCALER: u32 = 256;
+        const LSI: Kilohertz = Kilohertz(40);
+        let max_period = Milliseconds(MAX_PRESCALER * MAX_RELOAD / LSI.integer());
+        let mut expected_interval = Milliseconds(15000);
+        while expected_interval < max_period + 100.milliseconds() {
+            expected_interval = expected_interval + 100.milliseconds();
+
+            state.iwdg.feed();
+            state.iwdg.start(expected_interval);
+            let interval = state.iwdg.interval();
+            if interval < max_period {
+                // Test if the approximate value is reached (it is slightly lower most of the time)
+                assert!(
+                    interval.integer()
+                        >= expected_interval
+                            .integer()
+                            .saturating_sub(10.milliseconds().integer())
+                );
+            }
+        }
+        assert_eq!(state.iwdg.interval().integer(), max_period.integer());
+    }
+
     // It takes some time, until defmt_test exits.
-    // In this time, the wathcodg  can not be fed. So disable it in the last test.
+    // In this time, the watchdog can not be fed.
+    // set the value high enough, so this does not happen.
     #[test]
-    fn disable(state: &mut State) {
-        state.iwdg.stop();
+    fn finish(state: &mut State) {
+        state.iwdg.start(1000.milliseconds());
     }
 }