@@ -1472,7 +1472,12 @@ macro_rules! adc_common {
14721472 }
14731473
14741474 fn clock( & self , clocks: & Clocks ) -> Option <Hertz > {
1475- use crate :: pac:: rcc:: cfgr2:: ADC1PRES ;
1475+ #[ cfg( feature = "svd-f301" ) ]
1476+ use crate :: pac:: rcc:: cfgr2:: ADC1PRES as PRES ;
1477+
1478+ #[ cfg( not( feature = "svd-f301" ) ) ]
1479+ use crate :: pac:: rcc:: cfgr2:: ADC12PRES as PRES ;
1480+
14761481 use crate :: pac:: RCC ;
14771482 // SAFETY: atomic read with no side effects
14781483 let adc_pres = unsafe { & ( * RCC :: ptr( ) ) . cfgr2( ) . read( ) . $adcXYpres( ) } ;
@@ -1485,19 +1490,19 @@ macro_rules! adc_common {
14851490 Some ( pllclk) if !adc_pres. is_no_clock( ) => {
14861491 pllclk
14871492 / match adc_pres. variant( ) {
1488- Some ( ADC1PRES :: Div1 ) => 1 ,
1489- Some ( ADC1PRES :: Div2 ) => 2 ,
1490- Some ( ADC1PRES :: Div4 ) => 4 ,
1491- Some ( ADC1PRES :: Div6 ) => 6 ,
1492- Some ( ADC1PRES :: Div8 ) => 8 ,
1493- Some ( ADC1PRES :: Div10 ) => 10 ,
1494- Some ( ADC1PRES :: Div12 ) => 12 ,
1495- Some ( ADC1PRES :: Div16 ) => 16 ,
1496- Some ( ADC1PRES :: Div32 ) => 32 ,
1497- Some ( ADC1PRES :: Div64 ) => 64 ,
1498- Some ( ADC1PRES :: Div128 ) => 128 ,
1499- Some ( ADC1PRES :: Div256 ) => 256 ,
1500- Some ( ADC1PRES :: NoClock ) | None => 1 ,
1493+ Some ( PRES :: Div1 ) => 1 ,
1494+ Some ( PRES :: Div2 ) => 2 ,
1495+ Some ( PRES :: Div4 ) => 4 ,
1496+ Some ( PRES :: Div6 ) => 6 ,
1497+ Some ( PRES :: Div8 ) => 8 ,
1498+ Some ( PRES :: Div10 ) => 10 ,
1499+ Some ( PRES :: Div12 ) => 12 ,
1500+ Some ( PRES :: Div16 ) => 16 ,
1501+ Some ( PRES :: Div32 ) => 32 ,
1502+ Some ( PRES :: Div64 ) => 64 ,
1503+ Some ( PRES :: Div128 ) => 128 ,
1504+ Some ( PRES :: Div256 ) => 256 ,
1505+ Some ( PRES :: NoClock ) | None => 1 ,
15011506 }
15021507 }
15031508 _ => {
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