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Use variant for rcc
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‎src/rcc.rs

Lines changed: 82 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,10 @@
22
33
use core::cmp;
44

5-
use crate::stm32::{rcc, RCC};
6-
use cast::u32;
5+
use crate::stm32::{
6+
rcc::{self, cfgr},
7+
RCC,
8+
};
79

810
use crate::flash::ACR;
911
use crate::time::Hertz;
@@ -195,14 +197,14 @@ impl CFGR {
195197
feature = "stm32f303xe",
196198
feature = "stm32f398"
197199
)))]
198-
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRC_A) {
200+
fn calc_pll(&self) -> (u32, u32, cfgr::PLLSRC_A) {
199201
let pllsrcclk = self.hse.unwrap_or(HSI / 2);
200202
let pllmul = self.sysclk.unwrap_or(pllsrcclk) / pllsrcclk;
201203

202204
let pllsrc = if self.hse.is_some() {
203-
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
205+
cfgr::PLLSRC_A::HSE_DIV_PREDIV
204206
} else {
205-
rcc::cfgr::PLLSRC_A::HSI_DIV2
207+
cfgr::PLLSRC_A::HSI_DIV2
206208
};
207209
(pllsrcclk, pllmul, pllsrc)
208210
}
@@ -214,92 +216,108 @@ impl CFGR {
214216
feature = "stm32f303xe",
215217
feature = "stm32f398",
216218
))]
217-
fn calc_pll(&self) -> (u32, u32, rcc::cfgr::PLLSRC_A) {
219+
fn calc_pll(&self) -> (u32, u32, cfgr::PLLSRC_A) {
218220
let mut pllsrcclk = self.hse.unwrap_or(HSI / 2);
219221
let mut pllmul = self.sysclk.unwrap_or(pllsrcclk) / pllsrcclk;
220222

221223
let pllsrc = if self.hse.is_some() {
222-
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
224+
cfgr::PLLSRC_A::HSE_DIV_PREDIV
223225
} else if pllmul > 16 {
224226
pllmul /= 2;
225227
pllsrcclk *= 2;
226-
rcc::cfgr::PLLSRC_A::HSI_DIV_PREDIV
228+
cfgr::PLLSRC_A::HSI_DIV_PREDIV
227229
} else {
228-
rcc::cfgr::PLLSRC_A::HSI_DIV2
230+
cfgr::PLLSRC_A::HSI_DIV2
229231
};
230232
(pllsrcclk, pllmul, pllsrc)
231233
}
232234

233235
/// Returns a tuple containing the effective sysclk rate and optional pll settings.
234-
fn calc_sysclk(&self) -> (u32, Option<(u8, rcc::cfgr::PLLSRC_A)>) {
236+
fn calc_sysclk(&self) -> (u32, Option<(cfgr::PLLMUL_A, cfgr::PLLSRC_A)>) {
235237
let (pllsrcclk, pllmul, pllsrc) = self.calc_pll();
236238
if pllmul == 1 {
237239
return (pllsrcclk, None);
238240
}
239241

240242
let pllmul = cmp::min(cmp::max(pllmul, 2), 16);
241-
let sysclk = pllmul * pllsrcclk;
243+
let sysclk = pllsrcclk * pllmul;
242244
assert!(sysclk <= 72_000_000);
243245

244-
let pllmul_bits = pllmul as u8 - 2;
245-
(sysclk, Some((pllmul_bits, pllsrc)))
246+
// NOTE From<u8> for PLLMUL_A is not implemented
247+
let pllmul_mul = match pllmul as u8 {
248+
2 => cfgr::PLLMUL_A::MUL2,
249+
3 => cfgr::PLLMUL_A::MUL3,
250+
4 => cfgr::PLLMUL_A::MUL4,
251+
5 => cfgr::PLLMUL_A::MUL5,
252+
6 => cfgr::PLLMUL_A::MUL6,
253+
7 => cfgr::PLLMUL_A::MUL7,
254+
8 => cfgr::PLLMUL_A::MUL8,
255+
9 => cfgr::PLLMUL_A::MUL9,
256+
10 => cfgr::PLLMUL_A::MUL10,
257+
11 => cfgr::PLLMUL_A::MUL11,
258+
12 => cfgr::PLLMUL_A::MUL12,
259+
13 => cfgr::PLLMUL_A::MUL13,
260+
14 => cfgr::PLLMUL_A::MUL14,
261+
15 => cfgr::PLLMUL_A::MUL15,
262+
16 => cfgr::PLLMUL_A::MUL16,
263+
_ => unreachable!(),
264+
};
265+
(sysclk, Some((pllmul_mul, pllsrc)))
246266
}
247267

248268
/// Freezes the clock configuration, making it effective
249269
pub fn freeze(self, acr: &mut ACR) -> Clocks {
250270
let (sysclk, pll_options) = self.calc_sysclk();
251271

252-
let hpre_bits = self
272+
let (hpre_bits, hpre) = self
253273
.hclk
254274
.map(|hclk| match sysclk / hclk {
255275
0 => unreachable!(),
256-
1 => 0b0111,
257-
2 => 0b1000,
258-
3..=5 => 0b1001,
259-
6..=11 => 0b1010,
260-
12..=39 => 0b1011,
261-
40..=95 => 0b1100,
262-
96..=191 => 0b1101,
263-
192..=383 => 0b1110,
264-
_ => 0b1111,
276+
1 => (cfgr::HPRE_A::DIV1, 1),
277+
2 => (cfgr::HPRE_A::DIV2, 2),
278+
3..=5 => (cfgr::HPRE_A::DIV4, 4),
279+
6..=11 => (cfgr::HPRE_A::DIV8, 8),
280+
12..=39 => (cfgr::HPRE_A::DIV16, 16),
281+
40..=95 => (cfgr::HPRE_A::DIV64, 64),
282+
96..=191 => (cfgr::HPRE_A::DIV128, 128),
283+
192..=383 => (cfgr::HPRE_A::DIV256, 256),
284+
_ => (cfgr::HPRE_A::DIV512, 512),
265285
})
266-
.unwrap_or(0b0111);
286+
.unwrap_or((cfgr::HPRE_A::DIV1, 1));
267287

268-
let hclk = sysclk / (1 << (hpre_bits - 0b0111));
288+
let hclk: u32 = sysclk / hpre;
269289

270290
assert!(hclk <= 72_000_000);
271291

272-
let ppre1_bits = self
292+
let (ppre1_bits, ppre1) = self
273293
.pclk1
274294
.map(|pclk1| match hclk / pclk1 {
275295
0 => unreachable!(),
276-
1 => 0b011,
277-
2 => 0b100,
278-
3..=5 => 0b101,
279-
6..=11 => 0b110,
280-
_ => 0b111,
296+
1 => (cfgr::PPRE1_A::DIV1, 1),
297+
2 => (cfgr::PPRE1_A::DIV2, 2),
298+
3..=5 => (cfgr::PPRE1_A::DIV4, 4),
299+
6..=11 => (cfgr::PPRE1_A::DIV8, 8),
300+
_ => (cfgr::PPRE1_A::DIV16, 16),
281301
})
282-
.unwrap_or(0b011);
302+
.unwrap_or((cfgr::PPRE1_A::DIV1, 1));
283303

284-
let ppre1 = 1 << (ppre1_bits - 0b011);
285-
let pclk1 = hclk / u32(ppre1);
304+
let pclk1 = hclk / u32::from(ppre1);
286305

287306
assert!(pclk1 <= 36_000_000);
288307

289-
let ppre2_bits = self
308+
let (ppre2_bits, ppre2) = self
290309
.pclk2
291310
.map(|pclk2| match hclk / pclk2 {
292311
0 => unreachable!(),
293-
1 => 0b011,
294-
2 => 0b100,
295-
3..=5 => 0b101,
296-
6..=11 => 0b110,
297-
_ => 0b111,
312+
1 => (cfgr::PPRE2_A::DIV1, 1),
313+
2 => (cfgr::PPRE2_A::DIV2, 2),
314+
3..=5 => (cfgr::PPRE2_A::DIV4, 4),
315+
6..=11 => (cfgr::PPRE2_A::DIV8, 8),
316+
_ => (cfgr::PPRE2_A::DIV16, 16),
298317
})
299-
.unwrap_or(0b011);
318+
.unwrap_or((cfgr::PPRE2_A::DIV1, 1));
300319

301-
let ppre2 = 1 << (ppre2_bits - 0b011);
302-
let pclk2 = hclk / u32(ppre2);
320+
let pclk2 = hclk / u32::from(ppre2);
303321

304322
assert!(pclk2 <= 72_000_000);
305323

@@ -330,42 +348,39 @@ impl CFGR {
330348

331349
if self.hse.is_some() {
332350
// enable HSE and wait for it to be ready
351+
rcc.cr.modify(|_, w| w.hseon().on());
333352

334-
rcc.cr.modify(|_, w| w.hseon().set_bit());
335-
336-
while rcc.cr.read().hserdy().bit_is_clear() {}
353+
while rcc.cr.read().hserdy().is_not_ready() {}
337354
}
338355

339-
if let Some((pllmul_bits, pllsrc)) = pll_options {
356+
if let Some((pllmul_mul, pllsrc)) = pll_options {
340357
// enable PLL and wait for it to be ready
341358
rcc.cfgr
342-
.modify(|_, w| w.pllmul().bits(pllmul_bits).pllsrc().variant(pllsrc));
359+
.modify(|_, w| w.pllmul().variant(pllmul_mul).pllsrc().variant(pllsrc));
343360

344-
rcc.cr.modify(|_, w| w.pllon().set_bit());
361+
rcc.cr.modify(|_, w| w.pllon().on());
345362

346-
while rcc.cr.read().pllrdy().bit_is_clear() {}
363+
while rcc.cr.read().pllrdy().is_not_ready() {}
347364
}
348365

349366
// set prescalers and clock source
350-
rcc.cfgr.modify(|_, w| unsafe {
351-
set_usbpre(w, usbpre)
352-
.ppre2()
353-
.bits(ppre2_bits)
367+
rcc.cfgr.modify(|_, w| {
368+
usb_clocking::set_usbpre(w, usbpre);
369+
370+
w.ppre2()
371+
.variant(ppre2_bits)
354372
.ppre1()
355-
.bits(ppre1_bits)
373+
.variant(ppre1_bits)
356374
.hpre()
357-
.bits(hpre_bits)
358-
.sw()
359-
.bits(if pll_options.is_some() {
360-
// PLL
361-
0b10
362-
} else if self.hse.is_some() {
363-
// HSE
364-
0b01
365-
} else {
366-
// HSI
367-
0b00
368-
})
375+
.variant(hpre_bits);
376+
377+
if pll_options.is_some() {
378+
w.sw().pll()
379+
} else if self.hse.is_some() {
380+
w.sw().hse()
381+
} else {
382+
w.sw().hsi()
383+
}
369384
});
370385

371386
Clocks {

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