Merge pull request #172 from Sh3Rm4n/testsuite

Add tests for rcc via defmt-test and support defmt in hal

Author: Sh3Rm4n

.cargo/config.toml

@@ -1,7 +1,19 @@
+# Comment out probe-run runner and defmt link argument
+# to build and run tests based on probe-run and defmt
+#
+# TODO Support automatic link-arg switch based on features
+# [target.'cfg(feature = "..."'] are currently not supported.
+# Alternativly, we could create a build.rs and
+# at least set the link-arg. However this is unstabled
+# and only avaliable under the -Z extra-link-arg flag.
+# See https://github.com/rust-lang/cargo/pull/8441
 [target.thumbv7em-none-eabihf]
 runner = "arm-none-eabi-gdb"
+# Chip can be set via `--chip STM32F303VCTx` or `export PROBE_RUN_CHIP=STM32F303VCTx`
+# runner = "probe-run"
 rustflags = [
   "-C", "link-arg=-Tlink.x",
+  # "-C", "link-arg=-Tdefmt.x",
 ]
 
 [build]

.github/workflows/ci.yml

@@ -68,6 +68,29 @@ jobs:
           command: check
           args: --features=stm32f303xc,stm32-usbd,rt,can --lib --examples
 
+  check-tests:
+    name: Check Tests
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        test:
+          - rcc
+        mcu:
+          - stm32f303xc
+          - stm32f303xd
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          toolchain: stable
+          target: thumbv7em-none-eabihf
+          override: true
+          profile: minimal
+      - uses: actions-rs/cargo@v1
+        with:
+          command: check
+          args: --features=rt,defmt,${{ matrix.mcu }} --test ${{ matrix.test }}
+
   clippy:
     name: Clippy
     runs-on: ubuntu-latest

CHANGELOG.md

@@ -24,6 +24,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Support for HSE bypass and CSS ([#156](https://github.com/stm32-rs/stm32f3xx-hal/pull/156))
 - Impls for missing I2C pin definitions ([#164](https://github.com/stm32-rs/stm32f3xx-hal/pull/164))
 - Support I2C3 ([#164](https://github.com/stm32-rs/stm32f3xx-hal/pull/164))
+- Support for [`defmt`][defmt] ([#172](https://github.com/stm32-rs/stm32f3xx-hal/pull/172))
+  - Now [defmt][] features are available.
+  - Currently these are only used for panicking calls, like
+    `assert!` `panic!` or `unwrap()`. These are enabled using the [defmt][]
+    [filter][].
+  - For now [defmt][] is mostly intended for internal development and testing
+    to further reduce panicking calls in this crate.
+    The support of this feature is subject to change as the development
+    of [defmt][] is advancing.
+
+[defmt]: https://github.com/knurling-rs/defmt
+[filter]: https://defmt.ferrous-systems.com/filtering.html
 
 ### Changed
 

Cargo.toml

@@ -50,11 +50,18 @@ optional = true
 version = "1"
 default-features = false
 
+[dependencies.defmt]
+version = "0.1.2"
+optional = true
+
 [dev-dependencies]
 panic-semihosting = "0.5"
 usb-device = "0.2"
 usbd-serial = "0.1"
 cortex-m-semihosting = "0.3"
+panic-probe = "0.1.0"
+defmt-rtt = "0.1.0"
+defmt-test = "0.1.0"
 
 [features]
 default = ["unproven"]
@@ -95,6 +102,13 @@ stm32f328 = ["gpio-f333", "stm32f3/stm32f3x8", "device-selected"]
 stm32f358 = ["gpio-f303", "stm32f3/stm32f3x8", "device-selected"]
 stm32f398 = ["gpio-f303e", "stm32f3/stm32f3x8", "device-selected"]
 
+defmt-default = ["defmt"]
+defmt-trace = ["defmt"]
+defmt-debug = ["defmt"]
+defmt-info = ["defmt"]
+defmt-warn = ["defmt"]
+defmt-error = ["defmt"]
+
 [profile.dev]
 debug = true
 lto = true
@@ -139,3 +153,8 @@ required-features = ["stm32f303xc"]
 [[example]]
 name = "gpio_erased"
 required-features = ["rt", "stm32f303xc"]
+
+[[test]]
+name = "rcc"
+required-features = ["rt", "defmt"]
+harness = false

examples/adc.rs

@@ -3,7 +3,7 @@
 
 //! Example usage for ADC on STM32F303
 
-extern crate panic_semihosting;
+use panic_semihosting as _;
 
 use cortex_m_rt::entry;
 use cortex_m_semihosting::hprintln;

src/adc.rs

@@ -323,10 +323,10 @@ macro_rules! adc_hal {
                         operation_mode: None,
                     };
                     if !(this_adc.clocks_welldefined(clocks)) {
-                        panic!("Clock settings not well defined");
+                        crate::panic!("Clock settings not well defined");
                     }
                     if !(this_adc.enable_clock(ahb, adc_common)){
-                        panic!("Clock already enabled with a different setting");
+                        crate::panic!("Clock already enabled with a different setting");
                     }
                     this_adc.set_align(Align::default());
                     this_adc.calibrate();
@@ -365,7 +365,7 @@ macro_rules! adc_hal {
                 }
 
                 fn set_sequence_len(&mut self, len: u8) {
-                    assert!(len - 1 < 16, "ADC sequence length must be in 1..=16");
+                    crate::assert!(len - 1 < 16, "ADC sequence length must be in 1..=16");
                     self.rb.sqr1.modify(|_, w| w.l().bits(len - 1));
                 }
 
@@ -464,7 +464,7 @@ macro_rules! adc_hal {
                         16 => self.rb.smpr2.modify(|_, w| w.smp16().bits(smp.bitcode())),
                         17 => self.rb.smpr2.modify(|_, w| w.smp17().bits(smp.bitcode())),
                         18 => self.rb.smpr2.modify(|_, w| w.smp18().bits(smp.bitcode())),
-                        _ => unreachable!(),
+                        _ => crate::unreachable!(),
                     };
                 }
 

src/can.rs

@@ -188,7 +188,7 @@ impl embedded_hal_can::Filter for CanFilter {
     /// Constuct a mask filter. This method accepts two parameters, the mask which designates which
     /// bits are actually matched againts and the filter, with the actual bits to match.
     fn from_mask(mask: u32, filter: u32) -> Self {
-        assert!(
+        crate::assert!(
             mask < MAX_EXTENDED_ID,
             "Mask cannot have bits higher than 29"
         );
@@ -370,7 +370,7 @@ impl embedded_hal_can::Transmitter for CanTransmitter {
                 0 => can.tsr.read().tme0().bit_is_set(),
                 1 => can.tsr.read().tme1().bit_is_set(),
                 2 => can.tsr.read().tme2().bit_is_set(),
-                _ => unreachable!(),
+                _ => crate::unreachable!(),
             };
 
             if !free {
@@ -400,7 +400,7 @@ impl embedded_hal_can::Transmitter for CanTransmitter {
                             5 => tx.tdhr.modify(|_, w| w.data5().bits(*d)),
                             6 => tx.tdhr.modify(|_, w| w.data6().bits(*d)),
                             7 => tx.tdhr.modify(|_, w| w.data7().bits(*d)),
-                            _ => unreachable!(),
+                            _ => crate::unreachable!(),
                         }
                     }
                 }
@@ -447,7 +447,7 @@ impl Receiver for CanFifo {
                     5 => data[5] = data_high.data5().bits(),
                     6 => data[6] = data_high.data6().bits(),
                     7 => data[7] = data_high.data7().bits(),
-                    _ => unreachable!(),
+                    _ => crate::unreachable!(),
                 }
             }
 
@@ -504,15 +504,15 @@ impl Receiver for CanFifo {
             can.ffa1r.modify(|_, w| match self.idx {
                 0 => w.ffa0().clear_bit(),
                 1 => w.ffa0().set_bit(),
-                _ => unreachable!(),
+                _ => crate::unreachable!(),
             });
 
             let index = filter
                 .index
                 .unwrap_or_else(|| FILTER_INDEX.fetch_add(1, Ordering::Acquire))
                 as usize;
 
-            assert!(index < 28, "Filter index out of range");
+            crate::assert!(index < 28, "Filter index out of range");
 
             can.fb[index]
                 .fr1
@@ -554,7 +554,7 @@ impl CanFrame {
     ///
     /// This function will panic if length of `data` is greater than `8`
     pub fn new_data(id: CanId, data: &[u8]) -> CanFrame {
-        assert!((0..8).contains(&data.len()));
+        crate::assert!((0..8).contains(&data.len()));
 
         let mut frame = Self {
             id,

src/delay.rs

@@ -50,7 +50,7 @@ impl DelayUs<u32> for Delay {
     fn delay_us(&mut self, us: u32) {
         let rvr = us * (self.clocks.sysclk().0 / 1_000_000);
 
-        assert!(rvr < (1 << 24));
+        crate::assert!(rvr < (1 << 24));
 
         self.syst.set_reload(rvr);
         self.syst.clear_current();

src/dma.rs

@@ -61,7 +61,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
         // method we can call is `write_buffer`, which is allowed by
         // `WriteBuffer`'s safety requirements.
         let (ptr, len) = unsafe { buffer.write_buffer() };
-        let len = u16::try_from(len).expect("buffer is too large");
+        let len = crate::expect!(u16::try_from(len).ok(), "buffer is too large");
 
         // NOTE(unsafe) We are using the address of a 'static WriteBuffer here,
         // which is guaranteed to be safe for DMA.
@@ -88,7 +88,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
         // `&mut self` methods we can call, so we are safe according to
         // `ReadBuffer`'s safety requirements.
         let (ptr, len) = unsafe { buffer.read_buffer() };
-        let len = u16::try_from(len).expect("buffer is too large");
+        let len = crate::expect!(u16::try_from(len).ok(), "buffer is too large");
 
         // NOTE(unsafe) We are using the address of a 'static ReadBuffer here,
         // which is guaranteed to be safe for DMA.
@@ -110,7 +110,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
     where
         T: OnChannel<C>,
     {
-        assert!(!channel.is_enabled());
+        crate::assert!(!channel.is_enabled());
 
         atomic::compiler_fence(Ordering::Release);
 
@@ -128,13 +128,13 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
 
     /// Is this transfer complete?
     pub fn is_complete(&self) -> bool {
-        let inner = self.inner.as_ref().unwrap();
+        let inner = crate::unwrap!(self.inner.as_ref());
         inner.channel.event_occurred(Event::TransferComplete)
     }
 
     /// Stop this transfer and return ownership over its parts
     pub fn stop(mut self) -> (B, C, T) {
-        let mut inner = self.inner.take().unwrap();
+        let mut inner = crate::unwrap!(self.inner.take());
         inner.stop();
 
         (inner.buffer, inner.channel, inner.target)
@@ -280,7 +280,7 @@ pub trait Channel: private::Channel {
     /// Callers must ensure the given address is the address of a peripheral
     /// register that supports DMA.
     unsafe fn set_peripheral_address(&mut self, address: u32, inc: Increment) {
-        assert!(!self.is_enabled());
+        crate::assert!(!self.is_enabled());
 
         self.ch().par.write(|w| w.pa().bits(address));
         self.ch().cr.modify(|_, w| w.pinc().variant(inc.into()));
@@ -300,7 +300,7 @@ pub trait Channel: private::Channel {
     /// Callers must ensure the given address is a valid memory address
     /// that will remain valid as long as at is used by DMA.
     unsafe fn set_memory_address(&mut self, address: u32, inc: Increment) {
-        assert!(!self.is_enabled());
+        crate::assert!(!self.is_enabled());
 
         self.ch().mar.write(|w| w.ma().bits(address));
         self.ch().cr.modify(|_, w| w.minc().variant(inc.into()));
@@ -314,7 +314,7 @@ pub trait Channel: private::Channel {
     ///
     /// Panics if this channel is enabled.
     fn set_transfer_length(&mut self, len: u16) {
-        assert!(!self.is_enabled());
+        crate::assert!(!self.is_enabled());
 
         self.ch().ndtr.write(|w| w.ndt().bits(len));
     }
@@ -331,7 +331,7 @@ pub trait Channel: private::Channel {
             1 => BITS8,
             2 => BITS16,
             4 => BITS32,
-            s => panic!("unsupported word size: {}", s),
+            s => crate::panic!("unsupported word size: {:?}", s),
         };
 
         self.ch().cr.modify(|_, w| {

src/i2c.rs

@@ -120,7 +120,7 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
     {
         let freq = freq.into().0;
 
-        assert!(freq <= 1_000_000);
+        crate::assert!(freq <= 1_000_000);
 
         I2C::enable_clock(apb1);
 
@@ -171,11 +171,11 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
             (presc, scll, sclh, sdadel, scldel)
         };
 
-        assert!(presc < 16);
-        assert!(scldel < 16);
-        assert!(sdadel < 16);
-        let sclh = u8::try_from(sclh).unwrap();
-        let scll = u8::try_from(scll).unwrap();
+        crate::assert!(presc < 16);
+        crate::assert!(scldel < 16);
+        crate::assert!(sdadel < 16);
+        let sclh = crate::unwrap!(u8::try_from(sclh).ok());
+        let scll = crate::unwrap!(u8::try_from(scll).ok());
 
         // Configure for "fast mode" (400 KHz)
         // NOTE(write): writes all non-reserved bits.
@@ -211,7 +211,7 @@ where
     type Error = Error;
 
     fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
-        assert!(!buffer.is_empty());
+        crate::assert!(!buffer.is_empty());
 
         // Detect Bus busy
         if self.i2c.isr.read().busy().is_busy() {
@@ -339,7 +339,7 @@ where
     type Error = Error;
 
     fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
-        assert!(!bytes.is_empty() && !buffer.is_empty());
+        crate::assert!(!bytes.is_empty() && !buffer.is_empty());
 
         // Detect Bus busy
         if self.i2c.isr.read().busy().is_busy() {