Support 16 bit SPI (#107)

Add support for 16-bit SPI words

Author: zklapow

CHANGELOG.md

@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 ### Added
+
+- Support for 16-bit words with SPI ([#107](https://github.com/stm32-rs/stm32f3xx-hal/pull/107))
 - SPI support for reclock after initialization ([#98](https://github.com/stm32-rs/stm32f3xx-hal/pull/98))
 
 ## [v0.5.0] - 2020-07-21

src/spi.rs

@@ -4,7 +4,10 @@ use core::ptr;
 
 use crate::hal::spi::FullDuplex;
 pub use crate::hal::spi::{Mode, Phase, Polarity};
-use crate::pac::{SPI1, SPI2, SPI3};
+use crate::pac::{
+    spi1::cr2::{DS_A, FRXTH_A},
+    SPI1, SPI2, SPI3,
+};
 use crate::stm32::spi1;
 
 use crate::gpio::gpioa::{PA5, PA6, PA7};
@@ -47,6 +50,7 @@ use crate::rcc::APB1;
 ))]
 use crate::rcc::APB2;
 use crate::time::Hertz;
+use core::marker::PhantomData;
 
 /// SPI error
 #[derive(Debug)]
@@ -104,16 +108,33 @@ unsafe impl MosiPin<SPI2> for PB15<AF5> {}
 unsafe impl MosiPin<SPI3> for PB5<AF6> {}
 unsafe impl MosiPin<SPI3> for PC12<AF6> {}
 
+pub trait Word {
+    fn register_config() -> (FRXTH_A, DS_A);
+}
+
+impl Word for u8 {
+    fn register_config() -> (FRXTH_A, DS_A) {
+        (FRXTH_A::QUARTER, DS_A::EIGHTBIT)
+    }
+}
+
+impl Word for u16 {
+    fn register_config() -> (FRXTH_A, DS_A) {
+        (FRXTH_A::HALF, DS_A::SIXTEENBIT)
+    }
+}
+
 /// SPI peripheral operating in full duplex master mode
-pub struct Spi<SPI, PINS> {
+pub struct Spi<SPI, PINS, WORD = u8> {
     spi: SPI,
     pins: PINS,
+    _word: PhantomData<WORD>,
 }
 
 macro_rules! hal {
     ($($SPIX:ident: ($spiX:ident, $APBX:ident, $spiXen:ident, $spiXrst:ident, $pclkX:ident),)+) => {
         $(
-            impl<SCK, MISO, MOSI> Spi<$SPIX, (SCK, MISO, MOSI)> {
+            impl<SCK, MISO, MOSI, WORD> Spi<$SPIX, (SCK, MISO, MOSI), WORD> {
                 /// Configures the SPI peripheral to operate in full duplex master mode
                 pub fn $spiX<F>(
                     spi: $SPIX,
@@ -128,17 +149,20 @@ macro_rules! hal {
                     SCK: SckPin<$SPIX>,
                     MISO: MisoPin<$SPIX>,
                     MOSI: MosiPin<$SPIX>,
+                    WORD: Word,
                 {
                     // enable or reset $SPIX
                     apb2.enr().modify(|_, w| w.$spiXen().enabled());
                     apb2.rstr().modify(|_, w| w.$spiXrst().reset());
                     apb2.rstr().modify(|_, w| w.$spiXrst().clear_bit());
 
-                    // FRXTH: RXNE event is generated if the FIFO level is greater than or equal to
-                    //        8-bit
-                    // DS: 8-bit data size
-                    // SSOE: Slave Select output disabled
-                    spi.cr2.write(|w| w.frxth().quarter().ds().eight_bit().ssoe().disabled());
+                    let (frxth, ds) = WORD::register_config();
+                    spi.cr2.write(|w| {
+                        w.frxth().variant(frxth);
+                        w.ds().variant(ds);
+                        // Slave Select output disabled
+                        w.ssoe().disabled()
+                    });
 
                     // CPHA: phase
                     // CPOL: polarity
@@ -179,7 +203,7 @@ macro_rules! hal {
                             .unidirectional()
                     });
 
-                    Spi { spi, pins }
+                    Spi { spi, pins, _word: PhantomData }
                 }
 
                 /// Releases the SPI peripheral and associated pins
@@ -216,10 +240,10 @@ macro_rules! hal {
 
             }
 
-            impl<PINS> FullDuplex<u8> for Spi<$SPIX, PINS> {
+            impl<PINS, WORD> FullDuplex<WORD> for Spi<$SPIX, PINS, WORD> {
                 type Error = Error;
 
-                fn read(&mut self) -> nb::Result<u8, Error> {
+                fn read(&mut self) -> nb::Result<WORD, Error> {
                     let sr = self.spi.sr.read();
 
                     Err(if sr.ovr().is_overrun() {
@@ -229,17 +253,16 @@ macro_rules! hal {
                     } else if sr.crcerr().is_no_match() {
                         nb::Error::Other(Error::Crc)
                     } else if sr.rxne().is_not_empty() {
-                        // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
-                        // reading a half-word)
-                        return Ok(unsafe {
-                            ptr::read_volatile(&self.spi.dr as *const _ as *const u8)
-                        });
+                        let read_ptr = &self.spi.dr as *const _ as *const WORD;
+                        // NOTE(unsafe) read from register owned by this Spi struct
+                        let value = unsafe { ptr::read_volatile(read_ptr) };
+                        return Ok(value);
                     } else {
                         nb::Error::WouldBlock
                     })
                 }
 
-                fn send(&mut self, byte: u8) -> nb::Result<(), Error> {
+                fn send(&mut self, word: WORD) -> nb::Result<(), Error> {
                     let sr = self.spi.sr.read();
 
                     Err(if sr.ovr().is_overrun() {
@@ -249,18 +272,18 @@ macro_rules! hal {
                     } else if sr.crcerr().is_no_match() {
                         nb::Error::Other(Error::Crc)
                     } else if sr.txe().is_empty() {
-                        // NOTE(write_volatile) see note above
-                        unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, byte) }
+                        let write_ptr = &self.spi.dr as *const _ as *mut WORD;
+                        // NOTE(unsafe) write to register owned by this Spi struct
+                        unsafe { ptr::write_volatile(write_ptr, word) };
                         return Ok(());
                     } else {
                         nb::Error::WouldBlock
                     })
                 }
             }
 
-            impl<PINS> crate::hal::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
-
-            impl<PINS> crate::hal::blocking::spi::write::Default<u8> for Spi<$SPIX, PINS> {}
+            impl<PINS, WORD> crate::hal::blocking::spi::transfer::Default<WORD> for Spi<$SPIX, PINS, WORD> {}
+            impl<PINS, WORD> crate::hal::blocking::spi::write::Default<WORD> for Spi<$SPIX, PINS, WORD> {}
         )+
     }
 }