@@ -324,8 +324,7 @@ macro_rules! adc_hal {
324324 /// Software can use CkMode::SYNCDIV1 only if
325325 /// hclk and sysclk are the same. (see reference manual 15.3.3)
326326 fn clocks_welldefined( & self , clocks: Clocks ) -> bool {
327- if ( self . ckmode == CkMode :: SYNCDIV1 )
328- {
327+ if ( self . ckmode == CkMode :: SYNCDIV1 ) {
329328 clocks. hclk( ) . 0 == clocks. sysclk( ) . 0
330329 } else {
331330 true
@@ -348,7 +347,7 @@ macro_rules! adc_hal {
348347 }
349348
350349 fn set_sequence_len( & mut self , len: u8 ) {
351- debug_assert !( len <= 16 ) ;
350+ assert !( len - 1 < 16 , "ADC sequence length must be in 1..=16" ) ;
352351 self . rb. sqr1. modify( |_, w| w. l( ) . bits( len - 1 ) ) ;
353352 }
354353
@@ -362,7 +361,7 @@ macro_rules! adc_hal {
362361 }
363362
364363 fn disable( & mut self ) {
365- self . rb. cr. modify( |_, w| w. aden ( ) . clear_bit ( ) ) ;
364+ self . rb. cr. modify( |_, w| w. addis ( ) . disable ( ) ) ;
366365 }
367366
368367 /// Calibrate according to 15.3.8 in the Reference Manual
@@ -378,7 +377,7 @@ macro_rules! adc_hal {
378377 . adcaldif( ) . single_ended( )
379378 . adcal( ) . calibration( ) ) ;
380379
381- while ! self . rb. cr. read( ) . adcal( ) . is_complete ( ) { }
380+ while self . rb. cr. read( ) . adcal( ) . is_calibration ( ) { }
382381 }
383382
384383 fn wait_adc_clk_cycles( & self , cycles: u32 ) {
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