timer features

Author: burrbull

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
  - Add autoimplementations of `DMASet` [#614]
  - Simplify `gpio::Outport` [#611]
+ - rcc `enable_unchecked`, timer features
  - Split SPI master and slave implementations [#609]
  - Split USART and UART implementations [#608]
  - Add `lapce` editor settings [#601]

Cargo.toml

@@ -121,22 +121,22 @@ gpio-f401 = [
     "otg-fs",
     "sdio",
     "spi3", "spi4",
-    "tim2",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim9", "tim10", "tim11",
 ]
 gpio-f410 = [
     "dac",
     "fmpi2c1",
     "lptim1",
     "spi5",
+    "tim1", "tim5", "tim6", "tim9", "tim11",
 ]
 gpio-f411 = [
     "gpiod", "gpioe", # "gpioi",
     "i2c3",
     "otg-fs",
     "sdio",
-    "tim2",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim9", "tim10", "tim11",
     "spi3", "spi4", "spi5",
-
 ]
 gpio-f412 = [
     "gpiod", "gpioe", "gpiof", "gpiog",
@@ -150,7 +150,7 @@ gpio-f412 = [
     "rng",
     "sdio",
     "spi3", "spi4", "spi5",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3",
 ]
 gpio-f413 = [
@@ -169,7 +169,7 @@ gpio-f413 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8", "uart9", "uart10",
 ]
 gpio-f417 = [
@@ -186,7 +186,7 @@ gpio-f417 = [
     "rng",
     "sdio",
     "spi3",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5",
 ]
 gpio-f427 = [
@@ -204,7 +204,7 @@ gpio-f427 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5", "spi6",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8",
 ]
 gpio-f446 = [
@@ -224,7 +224,7 @@ gpio-f446 = [
     #"sdio",
     "spi3", "spi4",
     "spdifrx",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5",
 ]
 gpio-f469 = [
@@ -245,7 +245,7 @@ gpio-f469 = [
     "sai1",
     "sdio",
     "spi3", "spi4", "spi5", "spi6",
-    "tim2", "tim8",
+    "tim1", "tim2", "tim3", "tim4", "tim5", "tim6", "tim7", "tim8", "tim9", "tim10", "tim11", "tim12", "tim13", "tim14",
     "usart3", "uart4", "uart5", "uart7", "uart8",
 ]
 
@@ -296,8 +296,20 @@ spi4 = []
 spi5 = []
 spi6 = []
 spdifrx = []
+tim1 = []
 tim2 = []
+tim3 = []
+tim4 = []
+tim5 = []
+tim6 = []
+tim7 = []
 tim8 = []
+tim9 = []
+tim10 = []
+tim11 = []
+tim12 = []
+tim13 = []
+tim14 = []
 usart3 = []
 uart4 = []
 uart5 = []

src/dac.rs

@@ -6,7 +6,7 @@
 
 use crate::{
     gpio::{Analog, PA4, PA5},
-    pac::{DAC, RCC},
+    pac::DAC,
     rcc::{Enable, Reset},
 };
 

src/qei.rs

@@ -95,47 +95,42 @@ pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + General + CPin<0>
 }
 
 macro_rules! hal {
-    ($($TIM:ty,)+) => {
-        $(
-            impl Instance for $TIM {
-                fn setup_qei(&mut self) {
-                    // Configure TxC1 and TxC2 as captures
-                    #[cfg(not(feature = "gpio-f410"))]
-                    self.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());
-                    #[cfg(feature = "gpio-f410")]
-                    self.ccmr1_input()
-                        .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
-                    // enable and configure to capture on rising edge
-                    self.ccer.write(|w| {
-                        w.cc1e().set_bit().cc1p().clear_bit();
-                        w.cc2e().set_bit().cc2p().clear_bit()
-                    });
-                    self.smcr.write(|w| w.sms().encoder_mode_3());
-                    self.set_auto_reload(<$TIM as General>::Width::MAX as u32).unwrap();
-                    self.cr1.write(|w| w.cen().set_bit());
-                }
-
-                fn read_direction(&self) -> bool {
-                    self.cr1.read().dir().bit_is_clear()
-                }
+    ($TIM:ty) => {
+        impl Instance for $TIM {
+            fn setup_qei(&mut self) {
+                // Configure TxC1 and TxC2 as captures
+                #[cfg(not(feature = "gpio-f410"))]
+                self.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());
+                #[cfg(feature = "gpio-f410")]
+                self.ccmr1_input()
+                    .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
+                // enable and configure to capture on rising edge
+                self.ccer.write(|w| {
+                    w.cc1e().set_bit().cc1p().clear_bit();
+                    w.cc2e().set_bit().cc2p().clear_bit()
+                });
+                self.smcr.write(|w| w.sms().encoder_mode_3());
+                self.set_auto_reload(<$TIM as General>::Width::MAX as u32)
+                    .unwrap();
+                self.cr1.write(|w| w.cen().set_bit());
             }
-        )+
-    }
-}
 
-hal! {
-    pac::TIM1,
-    pac::TIM5,
+            fn read_direction(&self) -> bool {
+                self.cr1.read().dir().bit_is_clear()
+            }
+        }
+    };
 }
 
+#[cfg(feature = "tim1")]
+hal! { pac::TIM1 }
 #[cfg(feature = "tim2")]
-hal! {
-    pac::TIM2,
-    pac::TIM3,
-    pac::TIM4,
-}
-
+hal! { pac::TIM2 }
+#[cfg(feature = "tim3")]
+hal! { pac::TIM3 }
+#[cfg(feature = "tim4")]
+hal! { pac::TIM4 }
+#[cfg(feature = "tim5")]
+hal! { pac::TIM5 }
 #[cfg(feature = "tim8")]
-hal! {
-    pac::TIM8,
-}
+hal! { pac::TIM8 }

src/rng.rs

@@ -23,7 +23,6 @@
 use core::cmp;
 use core::mem;
 
-use crate::pac;
 use crate::pac::RNG;
 use crate::rcc::{Clocks, Enable, Reset};
 use core::num::NonZeroU32;
@@ -84,8 +83,10 @@ impl RngExt for RNG {
     fn constrain(self, clocks: &Clocks) -> Rng {
         cortex_m::interrupt::free(|_| {
             // enable RNG_CLK (peripheral clock)
-            RNG::enable_unchecked();
-            RNG::reset_unchecked();
+            unsafe {
+                RNG::enable_unchecked();
+                RNG::reset_unchecked();
+            }
 
             // verify the clock configuration is valid
             let hclk = clocks.hclk();