F7

Author: burrbull

.zed/settings.json

@@ -3,7 +3,7 @@
     "rust-analyzer": {
       "initialization_options": {
         "cargo": {
-          "features": ["defmt", "rtic1", "stm32f411"]
+          "features": ["defmt", "rtic1", "stm32f777"]
         },
         "check": {
           "allTargets": false,

src/rcc/f7/enable.rs

@@ -4,26 +4,19 @@ macro_rules! bus_enable {
     ($PER:ident => $en:ident) => {
         impl Enable for crate::pac::$PER {
             #[inline(always)]
-            fn enable(bus: &mut Self::Bus) {
-                bus.enr().modify(|_, w| w.$en().set_bit());
+            fn enable(rcc: &mut RCC) {
+                Self::Bus::enr(rcc).modify(|_, w| w.$en().set_bit());
                 // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
                 cortex_m::asm::dsb();
             }
             #[inline(always)]
-            fn disable(bus: &mut Self::Bus) {
-                bus.enr().modify(|_, w| w.$en().clear_bit());
+            fn disable(rcc: &mut RCC) {
+                Self::Bus::enr(rcc).modify(|_, w| w.$en().clear_bit());
             }
             #[inline(always)]
             fn is_enabled() -> bool {
-                Self::Bus::new().enr().read().$en().bit_is_set()
-            }
-            #[inline(always)]
-            unsafe fn enable_unchecked() {
-                Self::enable(&mut Self::Bus::new());
-            }
-            #[inline(always)]
-            unsafe fn disable_unchecked() {
-                Self::disable(&mut Self::Bus::new());
+                let rcc = RCC::ptr();
+                Self::Bus::enr(unsafe { &*rcc }).read().$en().bit_is_set()
             }
         }
     };
@@ -33,26 +26,22 @@ macro_rules! bus_lpenable {
     ($PER:ident => $lpen:ident) => {
         impl LPEnable for crate::pac::$PER {
             #[inline(always)]
-            fn low_power_enable(bus: &mut Self::Bus) {
-                bus.lpenr().modify(|_, w| w.$lpen().set_bit());
+            fn enable_in_low_power(rcc: &mut RCC) {
+                Self::Bus::lpenr(rcc).modify(|_, w| w.$lpen().set_bit());
                 // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
                 cortex_m::asm::dsb();
             }
             #[inline(always)]
-            fn low_power_disable(bus: &mut Self::Bus) {
-                bus.lpenr().modify(|_, w| w.$lpen().clear_bit());
-            }
-            #[inline(always)]
-            fn is_low_power_enabled() -> bool {
-                Self::Bus::new().lpenr().read().$lpen().bit_is_set()
-            }
-            #[inline(always)]
-            unsafe fn low_power_enable_unchecked() {
-                Self::enable(&mut Self::Bus::new());
+            fn disable_in_low_power(rcc: &mut RCC) {
+                Self::Bus::lpenr(rcc).modify(|_, w| w.$lpen().clear_bit());
             }
             #[inline(always)]
-            unsafe fn low_power_disable_unchecked() {
-                Self::disable(&mut Self::Bus::new());
+            fn is_enabled_in_low_power() -> bool {
+                let rcc = RCC::ptr();
+                Self::Bus::lpenr(unsafe { &*rcc })
+                    .read()
+                    .$lpen()
+                    .bit_is_set()
             }
         }
     };
@@ -61,14 +50,10 @@ macro_rules! bus_reset {
     ($PER:ident => $rst:ident) => {
         impl Reset for crate::pac::$PER {
             #[inline(always)]
-            fn reset(bus: &mut Self::Bus) {
-                let bits = bus.rstr().modify(|_, w| w.$rst().set_bit());
-                bus.rstr()
-                    .write(|w| unsafe { w.bits(bits).$rst().clear_bit() });
-            }
-            #[inline(always)]
-            unsafe fn reset_unchecked() {
-                Self::reset(&mut Self::Bus::new());
+            fn reset(rcc: &mut RCC) {
+                let rstr = Self::Bus::rstr(rcc);
+                let bits = rstr.modify(|_, w| w.$rst().set_bit());
+                rstr.write(|w| unsafe { w.bits(bits).$rst().clear_bit() });
             }
         }
     };

src/rcc/f7/mod.rs

@@ -9,6 +9,7 @@ use super::{BusClock, BusTimerClock, RccBus};
 #[cfg_attr(test, allow(unused_imports))]
 use micromath::F32Ext;
 
+use crate::pac::rcc::RegisterBlock as RccRB;
 use crate::pac::{rcc, FLASH, PWR, RCC};
 use fugit::{HertzU32 as Hertz, RateExtU32};
 
@@ -24,12 +25,6 @@ pub trait RccExt {
 impl RccExt for RCC {
     fn constrain(self) -> Rcc {
         Rcc {
-            ahb1: AHB1::new(),
-            ahb2: AHB2::new(),
-            ahb3: AHB3::new(),
-            apb1: APB1::new(),
-            apb2: APB2::new(),
-            bdcr: BDCR::new(),
             cfgr: CFGR {
                 hse: None,
                 hse_bypass: false,
@@ -64,48 +59,27 @@ impl RccExt for RCC {
 
 /// Constrained RCC peripheral
 pub struct Rcc {
-    /// Advanced High-Performance Bus 1 (AHB1) registers
-    pub ahb1: AHB1,
-    /// Advanced High-Performance Bus 2 (AHB2) registers
-    pub ahb2: AHB2,
-    /// Advanced High-Performance Bus 3 (AHB3) registers
-    pub ahb3: AHB3,
-
-    /// Advanced Peripheral Bus 1 (APB1) registers
-    pub apb1: APB1,
-    /// Advanced Peripheral Bus 2 (APB2) registers
-    pub apb2: APB2,
-    /// RCC Backup Domain
-    pub bdcr: BDCR,
     pub cfgr: CFGR,
 }
 
 macro_rules! bus_struct {
     ($($busX:ident => ($EN:ident, $en:ident, $LPEN:ident, $lpen:ident, $RST:ident, $rst:ident, $doc:literal),)+) => {
         $(
             #[doc = $doc]
-            pub struct $busX {
-                _0: (),
-            }
+            #[non_exhaustive]
+            pub struct $busX;
 
             impl $busX {
-                pub(crate) fn new() -> Self {
-                    Self { _0: () }
-                }
-
-                pub(crate) fn enr(&self) -> &rcc::$EN {
-                    // NOTE(unsafe) this proxy grants exclusive access to this register
-                    unsafe { (*RCC::ptr()).$en() }
+                pub(crate) fn enr(rcc: &RccRB) -> &rcc::$EN {
+                    rcc.$en()
                 }
 
-                pub(crate) fn lpenr(&self) -> &rcc::$LPEN {
-                    // NOTE(unsafe) this proxy grants exclusive access to this register
-                    unsafe { (*RCC::ptr()).$lpen() }
+                pub(crate) fn lpenr(rcc: &RccRB) -> &rcc::$LPEN {
+                    rcc.$lpen()
                 }
 
-                pub(crate) fn rstr(&self) -> &rcc::$RST {
-                    // NOTE(unsafe) this proxy grants exclusive access to this register
-                    unsafe { (*RCC::ptr()).$rst() }
+                pub(crate) fn rstr(rcc: &RccRB) -> &rcc::$RST {
+                    rcc.$rst()
                 }
             }
         )+
@@ -120,17 +94,6 @@ bus_struct! {
     AHB3 => (AHB3ENR, ahb3enr, AHB3LPENR, ahb3lpenr, AHB3RSTR, ahb3rstr, "Advanced High-performance Bus 3 (AHB3) registers"),
 }
 
-/// Backup Domain Control register (RCC_BDCR)
-pub struct BDCR {
-    _0: (),
-}
-
-impl BDCR {
-    pub(crate) fn new() -> Self {
-        Self { _0: () }
-    }
-}
-
 /*impl HSEClock {
     /// Provide HSE frequency.
     ///
@@ -255,19 +218,14 @@ pub enum MCO2 {
     Pll,
 }
 
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Eq)]
 enum VOSscale {
     PwrScale1,
     PwrScale2,
+    #[default]
     PwrScale3,
 }
 
-impl Default for VOSscale {
-    fn default() -> Self {
-        VOSscale::PwrScale3
-    }
-}
-
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Default)]
 struct InternalRCCConfig {
     hpre: u8,
@@ -605,7 +563,7 @@ impl CFGR {
                 }
                 + 1)
                 >> 1;
-            sysclk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
+            sysclk = (((base_clk * self.plln as u64 * one_over_m as u64)
                 >> Self::FIXED_POINT_RSHIFT)
                 * one_over_p as u64)
                 >> Self::FIXED_POINT_RSHIFT
@@ -621,7 +579,7 @@ impl CFGR {
                             ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
                         let one_over_q =
                             ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1;
-                        let pll48clk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
+                        let pll48clk = (((base_clk * self.plln as u64 * one_over_m as u64)
                             >> Self::FIXED_POINT_RSHIFT)
                             * one_over_q as u64)
                             >> Self::FIXED_POINT_RSHIFT
@@ -644,12 +602,11 @@ impl CFGR {
                                 }
                                 + 1)
                                 >> 1;
-                            let pll48clk =
-                                (((base_clk as u64 * self.pllsain as u64 * one_over_m as u64)
-                                    >> Self::FIXED_POINT_RSHIFT)
-                                    * one_over_p as u64)
-                                    >> Self::FIXED_POINT_RSHIFT
-                                    << Self::BASE_CLK_SHIFT;
+                            let pll48clk = (((base_clk * self.pllsain as u64 * one_over_m as u64)
+                                >> Self::FIXED_POINT_RSHIFT)
+                                * one_over_p as u64)
+                                >> Self::FIXED_POINT_RSHIFT
+                                << Self::BASE_CLK_SHIFT;
                             (48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk)
                         } else {
                             false
@@ -845,7 +802,7 @@ impl CFGR {
                 continue;
             }
             // See the comments around Self::FIXED_POINT_LSHIFT to see how this works.
-            let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;
+            let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / m + 1) >> 1;
             let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT)
                 * n as u64
                 * one_over_m as u64)
@@ -1333,66 +1290,83 @@ impl From<MCOPRE> for crate::pac::rcc::cfgr::MCO1PRE {
 /// Enable/disable peripheral
 pub trait Enable: RccBus {
     /// Enables peripheral
-    fn enable(bus: &mut Self::Bus);
+    fn enable(rcc: &mut RCC);
 
     /// Disables peripheral
-    fn disable(bus: &mut Self::Bus);
+    fn disable(rcc: &mut RCC);
 
     /// Check if peripheral enabled
     fn is_enabled() -> bool;
 
     /// Check if peripheral disabled
+    #[inline]
     fn is_disabled() -> bool {
         !Self::is_enabled()
     }
 
     /// # Safety
     ///
     /// Enables peripheral. Takes access to RCC internally
-    unsafe fn enable_unchecked();
+    unsafe fn enable_unchecked() {
+        let mut rcc = RCC::steal();
+        Self::enable(&mut rcc);
+    }
 
     /// # Safety
     ///
     /// Disables peripheral. Takes access to RCC internally
-    unsafe fn disable_unchecked();
+    unsafe fn disable_unchecked() {
+        let mut rcc = RCC::steal();
+        Self::disable(&mut rcc);
+    }
 }
 
-/// Enable/disable peripheral in low power mode
+/// Low power enable/disable peripheral
 pub trait LPEnable: RccBus {
     /// Enables peripheral in low power mode
-    fn low_power_enable(bus: &mut Self::Bus);
+    fn enable_in_low_power(rcc: &mut RCC);
 
     /// Disables peripheral in low power mode
-    fn low_power_disable(bus: &mut Self::Bus);
+    fn disable_in_low_power(rcc: &mut RCC);
 
     /// Check if peripheral enabled in low power mode
-    fn is_low_power_enabled() -> bool;
+    fn is_enabled_in_low_power() -> bool;
 
     /// Check if peripheral disabled in low power mode
-    fn is_low_power_disabled() -> bool {
-        !Self::is_low_power_enabled()
+    #[inline]
+    fn is_disabled_in_low_power() -> bool {
+        !Self::is_enabled_in_low_power()
     }
 
     /// # Safety
     ///
     /// Enables peripheral in low power mode. Takes access to RCC internally
-    unsafe fn low_power_enable_unchecked();
+    unsafe fn enable_in_low_power_unchecked() {
+        let mut rcc = RCC::steal();
+        Self::enable_in_low_power(&mut rcc);
+    }
 
     /// # Safety
     ///
     /// Disables peripheral in low power mode. Takes access to RCC internally
-    unsafe fn low_power_disable_unchecked();
+    unsafe fn disable_in_low_power_unchecked() {
+        let mut rcc = RCC::steal();
+        Self::disable_in_low_power(&mut rcc);
+    }
 }
 
 /// Reset peripheral
 pub trait Reset: RccBus {
     /// Resets peripheral
-    fn reset(bus: &mut Self::Bus);
+    fn reset(rcc: &mut RCC);
 
     /// # Safety
     ///
     /// Resets peripheral. Takes access to RCC internally
-    unsafe fn reset_unchecked();
+    unsafe fn reset_unchecked() {
+        let mut rcc = RCC::steal();
+        Self::reset(&mut rcc);
+    }
 }
 
 #[cfg(test)]