Skip to content

Commit 151fb18

Browse files
georgehosonogeorgehosono
committed
add trait bound to serial Instance and removed unneeded trait bound from associated impls
1 parent e0c29b9 commit 151fb18

File tree

4 files changed

+14
-54
lines changed

4 files changed

+14
-54
lines changed

‎CHANGELOG.md

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
77

88
## [Unreleased]
99

10+
- add trait bound `RegisterBlockImpl` to type `RegisterBlock` associated with `serial::Instance` [#732]
11+
- remove unneeded trait bound for methods that take in a `serial::Instance` and use the associated `RegisterBlock`
12+
1013
## [v0.20.0] - 2024-01-14
1114

1215
### Changed

‎src/serial/hal_02.rs

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,7 @@ mod nb {
1515
}
1616
}
1717

18-
impl<USART: Instance> Read<u8> for Rx<USART, u8>
19-
where
20-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
21-
{
18+
impl<USART: Instance> Read<u8> for Rx<USART, u8> {
2219
type Error = Error;
2320

2421
fn read(&mut self) -> nb::Result<u8, Self::Error> {
@@ -31,10 +28,7 @@ mod nb {
3128
/// If the UART/USART was configured with `WordLength::DataBits9`, the returned value will contain
3229
/// 9 received data bits and all other bits set to zero. Otherwise, the returned value will contain
3330
/// 8 received data bits and all other bits set to zero.
34-
impl<USART: Instance> Read<u16> for Rx<USART, u16>
35-
where
36-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
37-
{
31+
impl<USART: Instance> Read<u16> for Rx<USART, u16> {
3832
type Error = Error;
3933

4034
fn read(&mut self) -> nb::Result<u16, Self::Error> {
@@ -59,7 +53,6 @@ mod nb {
5953

6054
impl<USART: Instance> Write<u8> for Tx<USART, u8>
6155
where
62-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
6356
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
6457
{
6558
type Error = Error;
@@ -79,7 +72,6 @@ mod nb {
7972
/// will be transmitted and the other 8 bits will be ignored.
8073
impl<USART: Instance> Write<u16> for Tx<USART, u16>
8174
where
82-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
8375
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
8476
{
8577
type Error = Error;
@@ -102,7 +94,6 @@ mod blocking {
10294

10395
impl<USART: Instance> Write<u8> for Tx<USART, u8>
10496
where
105-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
10697
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
10798
{
10899
type Error = Error;
@@ -133,7 +124,6 @@ mod blocking {
133124

134125
impl<USART: Instance> Write<u16> for Tx<USART, u16>
135126
where
136-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
137127
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
138128
{
139129
type Error = Error;

‎src/serial/hal_1.rs

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,7 @@ mod nb {
3535
}
3636
}
3737

38-
impl<USART: Instance> Read<u8> for Rx<USART, u8>
39-
where
40-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
41-
{
38+
impl<USART: Instance> Read<u8> for Rx<USART, u8> {
4239
fn read(&mut self) -> nb::Result<u8, Self::Error> {
4340
unsafe { (*USART::ptr()).read_u8() }
4441
}
@@ -49,10 +46,7 @@ mod nb {
4946
/// If the UART/USART was configured with `WordLength::DataBits9`, the returned value will contain
5047
/// 9 received data bits and all other bits set to zero. Otherwise, the returned value will contain
5148
/// 8 received data bits and all other bits set to zero.
52-
impl<USART: Instance> Read<u16> for Rx<USART, u16>
53-
where
54-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
55-
{
49+
impl<USART: Instance> Read<u16> for Rx<USART, u16> {
5650
fn read(&mut self) -> nb::Result<u16, Self::Error> {
5751
unsafe { (*USART::ptr()).read_u16() }
5852
}
@@ -73,7 +67,6 @@ mod nb {
7367

7468
impl<USART: Instance> Write<u8> for Tx<USART, u8>
7569
where
76-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
7770
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
7871
{
7972
fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
@@ -91,7 +84,6 @@ mod nb {
9184
/// will be transmitted and the other 8 bits will be ignored.
9285
impl<USART: Instance> Write<u16> for Tx<USART, u16>
9386
where
94-
<USART as Instance>::RegisterBlock: RegisterBlockImpl,
9587
USART: Deref<Target = <USART as Instance>::RegisterBlock>,
9688
{
9789
fn write(&mut self, word: u16) -> nb::Result<(), Self::Error> {

‎src/serial/uart_impls.rs

Lines changed: 7 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ impl crate::Sealed for RegisterBlockUsart {}
2323

2424
// Implemented by all USART/UART instances
2525
pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + rcc::BusClock + CommonPins {
26-
type RegisterBlock;
26+
type RegisterBlock: RegisterBlockImpl;
2727

2828
#[doc(hidden)]
2929
fn ptr() -> *const Self::RegisterBlock;
@@ -343,10 +343,7 @@ where
343343
}
344344
}
345345

346-
impl<UART: Instance, WORD> RxISR for Rx<UART, WORD>
347-
where
348-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
349-
{
346+
impl<UART: Instance, WORD> RxISR for Rx<UART, WORD> {
350347
fn is_idle(&self) -> bool {
351348
unsafe { (*UART::ptr()).is_idle() }
352349
}
@@ -374,18 +371,14 @@ where
374371

375372
impl<UART: Instance, WORD> TxISR for Tx<UART, WORD>
376373
where
377-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
378374
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
379375
{
380376
fn is_tx_empty(&self) -> bool {
381377
self.usart.is_tx_empty()
382378
}
383379
}
384380

385-
impl<UART: Instance, WORD> RxListen for Rx<UART, WORD>
386-
where
387-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
388-
{
381+
impl<UART: Instance, WORD> RxListen for Rx<UART, WORD> {
389382
fn listen(&mut self) {
390383
unsafe { (*UART::ptr()).listen_rxne() }
391384
}
@@ -405,7 +398,6 @@ where
405398

406399
impl<UART: Instance, WORD> TxListen for Tx<UART, WORD>
407400
where
408-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
409401
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
410402
{
411403
fn listen(&mut self) {
@@ -419,7 +411,6 @@ where
419411

420412
impl<UART: Instance, WORD> crate::ClearFlags for Serial<UART, WORD>
421413
where
422-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
423414
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
424415
{
425416
type Flag = CFlag;
@@ -432,7 +423,6 @@ where
432423

433424
impl<UART: Instance, WORD> crate::ReadFlags for Serial<UART, WORD>
434425
where
435-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
436426
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
437427
{
438428
type Flag = Flag;
@@ -445,7 +435,6 @@ where
445435

446436
impl<UART: Instance, WORD> crate::Listen for Serial<UART, WORD>
447437
where
448-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
449438
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
450439
{
451440
type Event = Event;
@@ -479,7 +468,6 @@ where
479468

480469
impl<UART: Instance> fmt::Write for Tx<UART>
481470
where
482-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
483471
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
484472
{
485473
fn write_str(&mut self, s: &str) -> fmt::Result {
@@ -489,10 +477,7 @@ where
489477
}
490478
}
491479

492-
impl<UART: Instance> SerialExt for UART
493-
where
494-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
495-
{
480+
impl<UART: Instance> SerialExt for UART {
496481
fn serial<WORD>(
497482
self,
498483
pins: (impl Into<Self::Tx<PushPull>>, impl Into<Self::Rx<PushPull>>),
@@ -525,10 +510,7 @@ where
525510
}
526511
}
527512

528-
impl<UART: Instance, WORD> Serial<UART, WORD>
529-
where
530-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
531-
{
513+
impl<UART: Instance, WORD> Serial<UART, WORD> {
532514
pub fn tx(
533515
usart: UART,
534516
tx_pin: impl Into<UART::Tx<PushPull>>,
@@ -542,10 +524,7 @@ where
542524
}
543525
}
544526

545-
impl<UART: Instance, WORD> Serial<UART, WORD>
546-
where
547-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
548-
{
527+
impl<UART: Instance, WORD> Serial<UART, WORD> {
549528
pub fn rx(
550529
usart: UART,
551530
rx_pin: impl Into<UART::Rx<PushPull>>,
@@ -559,10 +538,7 @@ where
559538
}
560539
}
561540

562-
unsafe impl<UART: Instance> PeriAddress for Rx<UART, u8>
563-
where
564-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
565-
{
541+
unsafe impl<UART: Instance> PeriAddress for Rx<UART, u8> {
566542
#[inline(always)]
567543
fn address(&self) -> u32 {
568544
unsafe { (*UART::ptr()).peri_address() }
@@ -580,7 +556,6 @@ where
580556

581557
unsafe impl<UART: Instance> PeriAddress for Tx<UART, u8>
582558
where
583-
<UART as Instance>::RegisterBlock: RegisterBlockImpl,
584559
UART: Deref<Target = <UART as Instance>::RegisterBlock>,
585560
{
586561
#[inline(always)]

0 commit comments

Comments
 (0)