Skip to content

Commit 19a84c4

Browse files
committed
Serial flow control
1 parent ad969d2 commit 19a84c4

File tree

2 files changed

+64
-1
lines changed

2 files changed

+64
-1
lines changed

CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
99

1010
### Added
1111

12+
- Serial flow control enable
1213
- `i2c_scanner` example [#758]
1314
- Enable `sdio` for stm32f446
1415
- port LTDC implementation and example from stm32f7xx-hal [#731]

src/serial/uart_impls.rs

Lines changed: 63 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,10 @@ use crate::dma::{
1010
traits::{DMASet, PeriAddress},
1111
MemoryToPeripheral, PeripheralToMemory,
1212
};
13-
use crate::gpio::{alt::SerialAsync as CommonPins, NoPin, PushPull};
13+
use crate::gpio::{
14+
alt::{SerialAsync as CommonPins, SerialFlowControl},
15+
NoPin, PushPull,
16+
};
1417
use crate::rcc::{self, Clocks};
1518

1619
#[cfg(feature = "uart4")]
@@ -262,6 +265,20 @@ macro_rules! uartCommon {
262265
};
263266
}
264267

268+
pub trait RBFlowControlImpl {
269+
fn enable_rts(&self, state: bool);
270+
fn enable_cts(&self, state: bool);
271+
}
272+
273+
impl RBFlowControlImpl for RegisterBlockUsart {
274+
fn enable_rts(&self, state: bool) {
275+
self.cr3().modify(|_, w| w.rtse().bit(state));
276+
}
277+
fn enable_cts(&self, state: bool) {
278+
self.cr3().modify(|_, w| w.ctse().bit(state));
279+
}
280+
}
281+
265282
impl RegisterBlockImpl for RegisterBlockUsart {
266283
fn new<UART: Instance + crate::Ptr<RB = Self>, WORD>(
267284
uart: UART,
@@ -402,6 +419,23 @@ where {
402419
uartCommon! {}
403420
}
404421

422+
#[cfg(feature = "uart4")]
423+
#[cfg(not(any(
424+
feature = "gpio-f413",
425+
feature = "gpio-f417",
426+
feature = "gpio-f427",
427+
feature = "gpio-f446",
428+
feature = "gpio-f469"
429+
)))]
430+
impl RBFlowControlImpl for RegisterBlockUart {
431+
fn enable_rts(&self, state: bool) {
432+
self.cr3().modify(|_, w| w.rtse().bit(state));
433+
}
434+
fn enable_cts(&self, state: bool) {
435+
self.cr3().modify(|_, w| w.ctse().bit(state));
436+
}
437+
}
438+
405439
#[cfg(feature = "uart4")]
406440
impl RegisterBlockImpl for RegisterBlockUart {
407441
fn new<UART: Instance + crate::Ptr<RB = Self>, WORD>(
@@ -509,6 +543,34 @@ where {
509543
uartCommon! {}
510544
}
511545

546+
impl<UART: Instance + SerialFlowControl, WORD> Serial<UART, WORD>
547+
where
548+
UART::RegisterBlock: RBFlowControlImpl,
549+
{
550+
pub fn with_rts(self, rts: impl Into<UART::Rts>) -> Self {
551+
self.rx.usart.enable_rts(true);
552+
let _rts = rts.into();
553+
self
554+
}
555+
pub fn with_cts(self, cts: impl Into<UART::Cts>) -> Self {
556+
self.tx.usart.enable_cts(true);
557+
let _cts = cts.into();
558+
self
559+
}
560+
pub fn enable_request_to_send(&mut self) {
561+
self.rx.usart.enable_rts(true);
562+
}
563+
pub fn disable_request_to_send(&mut self) {
564+
self.rx.usart.enable_rts(false);
565+
}
566+
pub fn enable_clear_to_send(&mut self) {
567+
self.tx.usart.enable_cts(true);
568+
}
569+
pub fn disable_clear_to_send(&mut self) {
570+
self.tx.usart.enable_cts(false);
571+
}
572+
}
573+
512574
impl<UART: Instance, WORD> RxISR for Serial<UART, WORD>
513575
where
514576
Rx<UART, WORD>: RxISR,

0 commit comments

Comments
 (0)