split USART and UART impls

Author: burrbull

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+ - Split USART and UART implementations
  - Add `lapce` editor settings [#601]
  - Use `enum`s for alternate peripheral pins [#594]
  - Added missing U(S)ART DMA traits for HAL serial types [#593]

src/dma/traits.rs

@@ -1,4 +1,6 @@
 use super::*;
+#[cfg(feature = "uart4")]
+use crate::uart;
 use crate::{
     adc::Adc,
     i2c,
@@ -500,9 +502,9 @@ address!((pac::SPI4, dr, u8),);
     feature = "gpio-f469",
 ))]
 dma_map!(
-    (Stream0<DMA1>, 4, pac::UART5 | serial::Rx<pac::UART5>, PeripheralToMemory), //UART5_RX
-    (Stream2<DMA1>, 4, pac::UART4 | serial::Rx<pac::UART4>, PeripheralToMemory), //UART4_RX
-    (Stream4<DMA1>, 4, pac::UART4 | serial::Tx<pac::UART4>, MemoryToPeripheral), //UART4_TX
+    (Stream0<DMA1>, 4, pac::UART5 | uart::Rx<pac::UART5>, PeripheralToMemory), //UART5_RX
+    (Stream2<DMA1>, 4, pac::UART4 | uart::Rx<pac::UART4>, PeripheralToMemory), //UART4_RX
+    (Stream4<DMA1>, 4, pac::UART4 | uart::Tx<pac::UART4>, MemoryToPeripheral), //UART4_TX
     //(Stream6<DMA1>, 7, pac::DAC2, MemoryToPeripheral), //DAC2
 );
 
@@ -618,7 +620,7 @@ address!(
     feature = "gpio-f469",
 ))]
 dma_map!(
-    (Stream7<DMA1>, 4, pac::UART5 | serial::Tx<pac::UART5>, MemoryToPeripheral), //UART5_TX
+    (Stream7<DMA1>, 4, pac::UART5 | uart::Tx<pac::UART5>, MemoryToPeripheral), //UART5_TX
     (Stream0<DMA2>, 2, pac::ADC3 | Adc<pac::ADC3>, PeripheralToMemory), //ADC3
     (Stream1<DMA2>, 2, pac::ADC3 | Adc<pac::ADC3>, PeripheralToMemory), //ADC3
     (Stream2<DMA2>, 1, pac::ADC2 | Adc<pac::ADC2>, PeripheralToMemory), //ADC2
@@ -760,24 +762,24 @@ address!((pac::QUADSPI, dr, u32),);
 
 #[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469",))]
 dma_map!(
-    (Stream0<DMA1>, 5, pac::UART8 | serial::Tx<pac::UART8>, MemoryToPeripheral), //UART8_TX
-    (Stream1<DMA1>, 5, pac::UART7 | serial::Tx<pac::UART7>, MemoryToPeripheral), //UART7_TX
-    (Stream3<DMA1>, 5, pac::UART7 | serial::Rx<pac::UART7>, PeripheralToMemory), //UART7_RX
-    (Stream6<DMA1>, 5, pac::UART8 | serial::Rx<pac::UART8>, PeripheralToMemory), //UART8_RX
+    (Stream0<DMA1>, 5, pac::UART8 | uart::Tx<pac::UART8>, MemoryToPeripheral), //UART8_TX
+    (Stream1<DMA1>, 5, pac::UART7 | uart::Tx<pac::UART7>, MemoryToPeripheral), //UART7_TX
+    (Stream3<DMA1>, 5, pac::UART7 | uart::Rx<pac::UART7>, PeripheralToMemory), //UART7_RX
+    (Stream6<DMA1>, 5, pac::UART8 | uart::Rx<pac::UART8>, PeripheralToMemory), //UART8_RX
 );
 
 #[cfg(any(feature = "gpio-f413", feature = "gpio-f427", feature = "gpio-f469",))]
 address!((pac::UART7, dr, u8), (pac::UART8, dr, u8),);
 
 #[cfg(feature = "gpio-f413")]
 dma_map!(
-    (Stream7<DMA1>, 8, pac::UART5 | serial::Tx<pac::UART5>, MemoryToPeripheral), //UART5_TX
-    (Stream0<DMA2>, 1, pac::UART9 | serial::Tx<pac::UART9>, MemoryToPeripheral), //UART9_TX
-    (Stream0<DMA2>, 5, pac::UART10 | serial::Rx<pac::UART10>, PeripheralToMemory), //UART10_RX
-    (Stream3<DMA2>, 9, pac::UART10 | serial::Rx<pac::UART10>, PeripheralToMemory), //UART10_RX:DMA_CHANNEL_9
-    (Stream5<DMA2>, 9, pac::UART10 | serial::Tx<pac::UART10>, MemoryToPeripheral), //UART10_TX
-    (Stream7<DMA2>, 0, pac::UART9 | serial::Rx<pac::UART9>, PeripheralToMemory), //UART9_RX
-    (Stream7<DMA2>, 6, pac::UART10 | serial::Tx<pac::UART10>, MemoryToPeripheral), //UART10_TX:DMA_CHANNEL_6
+    (Stream7<DMA1>, 8, pac::UART5 | uart::Tx<pac::UART5>, MemoryToPeripheral), //UART5_TX
+    (Stream0<DMA2>, 1, pac::UART9 | uart::Tx<pac::UART9>, MemoryToPeripheral), //UART9_TX
+    (Stream0<DMA2>, 5, pac::UART10 | uart::Rx<pac::UART10>, PeripheralToMemory), //UART10_RX
+    (Stream3<DMA2>, 9, pac::UART10 | uart::Rx<pac::UART10>, PeripheralToMemory), //UART10_RX:DMA_CHANNEL_9
+    (Stream5<DMA2>, 9, pac::UART10 | uart::Tx<pac::UART10>, MemoryToPeripheral), //UART10_TX
+    (Stream7<DMA2>, 0, pac::UART9 | uart::Rx<pac::UART9>, PeripheralToMemory), //UART9_RX
+    (Stream7<DMA2>, 6, pac::UART10 | uart::Tx<pac::UART10>, MemoryToPeripheral), //UART10_TX:DMA_CHANNEL_6
     //(pac::DMA2, Stream6, 2, IN<pac::AES>, MemoryToPeripheral), //AES_IN
     //(pac::DMA2, Stream5, 2, OUT<pac::AES>, PeripheralToMemory), //AES_OUT
 );

src/fmpi2c.rs

@@ -48,9 +48,7 @@ pub enum FmpMode {
 
 impl FmpMode {
     pub fn standard(frequency: Hertz) -> Self {
-        Self::Standard {
-            frequency: frequency.into(),
-        }
+        Self::Standard { frequency }
     }
 
     pub fn fast(frequency: Hertz) -> Self {

src/fmpi2c/hal_1.rs

@@ -51,10 +51,10 @@ mod blocking {
             todo!()
         }
 
-        fn transaction<'a>(
+        fn transaction(
             &mut self,
             _addr: u8,
-            _operations: &mut [Operation<'a>],
+            _operations: &mut [Operation<'_>],
         ) -> Result<(), Self::Error> {
             todo!()
         }

src/gpio/alt.rs

@@ -1260,6 +1260,11 @@ pub mod usart1 {
             PB3<7>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::USART1 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 pub mod usart2 {
@@ -1298,6 +1303,11 @@ pub mod usart2 {
             PD6<7>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::USART2 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "usart3")]
@@ -1360,6 +1370,11 @@ pub mod usart3 {
             PD9<7>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::USART3 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 pub mod usart6 {
@@ -1397,6 +1412,11 @@ pub mod usart6 {
             PG9<8>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::USART6 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart4")]
@@ -1446,6 +1466,11 @@ pub mod uart4 {
             PC11<8>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART4 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart5")]
@@ -1485,6 +1510,11 @@ pub mod uart5 {
             PB12<11>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART5 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart7")]
@@ -1552,6 +1582,11 @@ pub mod uart7 {
             PB3<8>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART7 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart8")]
@@ -1593,6 +1628,11 @@ pub mod uart8 {
             PF8<8>,
         ],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART8 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart9")]
@@ -1603,6 +1643,11 @@ pub mod uart9 {
         <Tx> for no:NoPin, [PD15<11>, PG1<11>,],
         <Rx> for no:NoPin, [PD14<11>, PG0<11>,],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART9 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "uart10")]
@@ -1613,6 +1658,11 @@ pub mod uart10 {
         <Tx> for no:NoPin, [PE3<11>, PG12<11>,],
         <Rx> for no:NoPin, [PE2<11>, PG11<11>,],
     }
+
+    impl crate::serial::CommonPins for crate::pac::UART10 {
+        type RxPin = Rx;
+        type TxPin = Tx;
+    }
 }
 
 #[cfg(feature = "sdio")]

src/lib.rs

@@ -172,6 +172,9 @@ pub mod time;
 #[cfg(feature = "device-selected")]
 pub mod timer;
 #[cfg(feature = "device-selected")]
+#[cfg(feature = "uart4")]
+pub mod uart;
+#[cfg(feature = "device-selected")]
 pub mod watchdog;
 
 #[cfg(feature = "device-selected")]

src/prelude.rs

@@ -86,3 +86,5 @@ pub use crate::timer::PwmExt as _stm32f4xx_hal_timer_PwmExt;
 pub use crate::timer::SysMonoTimerExt as _stm32f4xx_hal_timer_SysMonoTimerExt;
 pub use crate::timer::SysTimerExt as _stm32f4xx_hal_timer_SysCounterExt;
 pub use crate::timer::TimerExt as _stm32f4xx_hal_timer_TimerExt;
+#[cfg(feature = "uart4")]
+pub use crate::uart::SerialExt as _stm32f4xx_hal_uart_SerialExt;