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Merge pull request #830 from faunel/timer_input_capture
Added support for Input Capture timer mode for frequency and pulse duration measurement
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CHANGELOG.md

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@@ -15,6 +15,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Use `write` instead of `modify` to clear flags [#829]
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- Bump `stm32f4-staging` to 0.18, update other dependencies [#831]
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- `serial` mod refactor [#833] [#839]
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- Add "capture" support for timers [#830]
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- FMPI2c APB timings [#770]
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- Fefactor FMPI2c `embedded-hal` implementations [#784]
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- remove `NoPin`, use `Option` instead [#813]
@@ -23,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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[#784]: https://github.com/stm32-rs/stm32f4xx-hal/pull/784
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[#813]: https://github.com/stm32-rs/stm32f4xx-hal/pull/813
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[#829]: https://github.com/stm32-rs/stm32f4xx-hal/pull/829
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[#830]: https://github.com/stm32-rs/stm32f4xx-hal/pull/830
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[#831]: https://github.com/stm32-rs/stm32f4xx-hal/pull/831
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[#832]: https://github.com/stm32-rs/stm32f4xx-hal/pull/832
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[#833]: https://github.com/stm32-rs/stm32f4xx-hal/pull/833

Cargo.toml

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@@ -781,3 +781,7 @@ required-features = []
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[[example]]
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name = "fmc-sdram"
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required-features = ["stm32f469", "stm32-fmc"]
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[[example]]
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name = "rtic2-timer-input-capture"
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required-features = ["rtic2"]

examples/rtic2-timer-input-capture.rs

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#![no_main]
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#![no_std]
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use defmt_rtt as _;
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use panic_probe as _;
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use stm32f4xx_hal::{
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pac,
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pac::{TIM2, TIM5},
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prelude::*,
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rcc,
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timer::{CaptureChannel, CaptureHzManager, CapturePolarity, Event, Flag, PwmChannel, Timer},
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};
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use rtic::app;
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#[app(device = pac, dispatchers = [USART1], peripherals = true)]
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mod app {
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use super::*;
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#[shared]
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struct Shared {}
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#[local]
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struct Local {
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tim5: CaptureHzManager<TIM5>,
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ch1: CaptureChannel<TIM5, 0>,
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}
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#[init]
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fn init(ctx: init::Context) -> (Shared, Local) {
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let dp = ctx.device;
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let mut rcc = dp.RCC.freeze(rcc::Config::hsi().sysclk(48.MHz()));
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let gpioa = dp.GPIOA.split(&mut rcc);
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// Configuration of TIM2 in PWM mode
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let timer = Timer::new(dp.TIM2, &mut rcc);
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let (_, (ch1, ..)) = timer.pwm_hz(893.Hz());
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let mut tim_2: PwmChannel<TIM2, 0> = ch1.with(gpioa.pa5);
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tim_2.set_duty(50);
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tim_2.enable();
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// It is necessary to connect pins PA0 and PA5 through a resistor of 1 kΩ - 10 kΩ
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// Configuration of TIM5 in input capture mode
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let (mut tim5, (ch1, ..)) = Timer::new(dp.TIM5, &mut rcc).capture_hz(48.MHz());
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let mut ch1 = ch1.with(gpioa.pa0);
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tim5.listen(Event::C1);
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ch1.set_polarity(CapturePolarity::ActiveHigh);
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ch1.enable();
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defmt::info!("Start");
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(Shared {}, Local { tim5, ch1 })
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}
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#[task(binds = TIM5, local = [tim5, ch1, prev_capture: u32 = 0], priority = 3)]
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fn tim5_interrupt(cx: tim5_interrupt::Context) {
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if cx.local.tim5.flags().contains(Flag::C1) {
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let timer_clock = cx.local.tim5.get_timer_clock();
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let max_auto_reload = cx.local.tim5.get_max_auto_reload();
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let current_capture = cx.local.ch1.get_capture();
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let delta = if current_capture >= *cx.local.prev_capture {
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current_capture - *cx.local.prev_capture
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} else {
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(max_auto_reload - *cx.local.prev_capture) + current_capture
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};
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let freq = timer_clock as f32 / delta as f32;
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defmt::info!("Freq: {} Hz", freq); // Output = Freq: 893.00665 Hz
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*cx.local.prev_capture = current_capture;
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cx.local.tim5.clear_flags(Flag::C1);
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}
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}
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}

src/flash.rs

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@@ -50,7 +50,7 @@ pub trait FlashExt {
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}
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/// Unlock flash for erasing/programming until this method's
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/// result is dropped
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fn unlocked(&mut self) -> UnlockedFlash;
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fn unlocked(&mut self) -> UnlockedFlash<'_>;
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// Returns true if flash is in dual bank organization
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fn dual_bank(&self) -> bool;
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/// Returns flash memory sector of a given offset. Returns none if offset is out of range.

src/pacext/uart.rs

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@@ -149,7 +149,7 @@ mod reg {
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fn psc(r: &R<Self>) -> usart1::gtpr::PSC_R;
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}
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pub trait GtprW: RegisterSpec<Ux = u16> + Writable + Resettable + Sized {
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fn psc(w: &mut W<Self>) -> usart1::gtpr::PSC_W<Self>;
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fn psc(w: &mut W<Self>) -> usart1::gtpr::PSC_W<'_, Self>;
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}
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}
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src/serial.rs

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@@ -18,6 +18,7 @@ use core::fmt;
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use core::marker::PhantomData;
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use enumflags2::BitFlags;
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#[allow(unused)]
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use crate::pacext::uart::UartRB;
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mod hal_02;
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mod hal_1;

src/serial/hal_02.rs

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mod nb {
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use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
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#[allow(unused)]
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use super::super::RegisterBlockImpl;
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use super::super::{Error, Instance, Rx, Serial, Tx};
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use embedded_hal_02::serial::{Read, Write};
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impl<USART: Instance, WORD> Read<WORD> for Serial<USART, WORD>
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mod blocking {
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use core::ops::Deref;
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use super::super::{Error, Instance, RegisterBlockImpl, Serial, Tx};
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#[allow(unused)]
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use super::super::RegisterBlockImpl;
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use super::super::{Error, Instance, Serial, Tx};
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use embedded_hal_02::blocking::serial::Write;
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impl<USART: Instance> Write<u8> for Tx<USART, u8> {

src/serial/hal_1.rs

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mod nb {
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use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
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#[allow(unused)]
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use super::super::RegisterBlockImpl;
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use super::super::{Error, Instance, Rx, Serial, Tx};
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use embedded_hal_nb::serial::{ErrorKind, Read, Write};
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impl embedded_hal_nb::serial::Error for Error {
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}
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mod io {
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use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
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#[allow(unused)]
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use super::super::RegisterBlockImpl;
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use super::super::{Error, Instance, Rx, Serial, Tx};
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use embedded_io::Write;
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impl embedded_io::Error for Error {

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