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burrbullburrbull
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Speed::VeryHigh by default
1 parent a6efa0c commit 39e08c3

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4 files changed

+225
-307
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4 files changed

+225
-307
lines changed

‎CHANGELOG.md

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
99

1010
### Changed
1111

12+
- Set `Speed::VeryHigh` default for FMC, SDIO & OTG_HS_ULPI pins, clean into_alternate in examples [#632]
1213
- Join `Serial`, `Rx`, `Tx` for `USART` and `UART` again. Make inner traits with different implementation for USART and UART. [#636]
1314

1415
### Fixed
1516

16-
- map `$SpiSlave` into `SpiSlave` struct in `spi!` macro [#635]
17+
- map `$SpiSlave` into `SpiSlave` struct in `spi!` macro [#635]
1718

19+
[#632]: https://github.com/stm32-rs/stm32f4xx-hal/pull/632
1820
[#635]: https://github.com/stm32-rs/stm32f4xx-hal/pull/635
21+
[#636]: https://github.com/stm32-rs/stm32f4xx-hal/pull/636
1922

2023
## [v0.16.0] - 2023-05-07
2124

‎src/fsmc_lcd/pins.rs

Lines changed: 12 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -16,50 +16,21 @@
1616
//! * Write enable
1717
1818
use crate::gpio::alt::fsmc as alt;
19-
use crate::gpio::{PinSpeed, Speed};
2019

2120
use super::sealed;
2221
use super::{Lcd, SubBank1};
2322
use crate::fsmc_lcd::{SubBank2, SubBank3, SubBank4};
2423

2524
/// One, two, three, or four address pins
26-
pub trait AddressPins: sealed::Sealed {
27-
fn set_high_speed(&mut self);
28-
}
25+
pub trait AddressPins: sealed::Sealed {}
2926

3027
// Implement AddressPins for one address pin and tuples of two, three, and four
31-
impl AddressPins for alt::Address {
32-
#[inline(always)]
33-
fn set_high_speed(&mut self) {
34-
self.set_speed(Speed::VeryHigh);
35-
}
36-
}
37-
impl AddressPins for (alt::Address, alt::Address) {
38-
#[inline(always)]
39-
fn set_high_speed(&mut self) {
40-
self.0.set_speed(Speed::VeryHigh);
41-
self.1.set_speed(Speed::VeryHigh);
42-
}
43-
}
28+
impl AddressPins for alt::Address {}
29+
impl AddressPins for (alt::Address, alt::Address) {}
4430
impl sealed::Sealed for (alt::Address, alt::Address) {}
45-
impl AddressPins for (alt::Address, alt::Address, alt::Address) {
46-
#[inline(always)]
47-
fn set_high_speed(&mut self) {
48-
self.0.set_speed(Speed::VeryHigh);
49-
self.1.set_speed(Speed::VeryHigh);
50-
self.2.set_speed(Speed::VeryHigh);
51-
}
52-
}
31+
impl AddressPins for (alt::Address, alt::Address, alt::Address) {}
5332
impl sealed::Sealed for (alt::Address, alt::Address, alt::Address) {}
54-
impl AddressPins for (alt::Address, alt::Address, alt::Address, alt::Address) {
55-
#[inline(always)]
56-
fn set_high_speed(&mut self) {
57-
self.0.set_speed(Speed::VeryHigh);
58-
self.1.set_speed(Speed::VeryHigh);
59-
self.2.set_speed(Speed::VeryHigh);
60-
self.3.set_speed(Speed::VeryHigh);
61-
}
62-
}
33+
impl AddressPins for (alt::Address, alt::Address, alt::Address, alt::Address) {}
6334
impl sealed::Sealed for (alt::Address, alt::Address, alt::Address, alt::Address) {}
6435

6536
macro_rules! conjure {
@@ -118,7 +89,6 @@ pub trait ChipSelectPins: sealed::Sealed {
11889
/// One, two, three, or four `Lcd<_>` objects associated with the sub-bank(s) that these pin(s)
11990
/// control
12091
type Lcds: sealed::Conjure;
121-
fn set_high_speed(&mut self);
12292
}
12393

12494
// The set of 4 chip selects has 15 subsets (excluding the empty set):
@@ -143,13 +113,6 @@ macro_rules! chipselect {
143113
$(
144114
impl ChipSelectPins for ($(alt::$Ne),+) {
145115
type Lcds = ($(Lcd<$sb>),+);
146-
147-
#[inline(always)]
148-
fn set_high_speed(&mut self) {
149-
$(
150-
self.$i.set_speed(Speed::VeryHigh);
151-
)+
152-
}
153116
}
154117
impl sealed::Sealed for ($(alt::$Ne),+) {}
155118
)+
@@ -158,35 +121,15 @@ macro_rules! chipselect {
158121

159122
impl ChipSelectPins for alt::Ne1 {
160123
type Lcds = Lcd<SubBank1>;
161-
162-
#[inline(always)]
163-
fn set_high_speed(&mut self) {
164-
self.set_speed(Speed::VeryHigh);
165-
}
166124
}
167125
impl ChipSelectPins for alt::Ne2 {
168126
type Lcds = Lcd<SubBank2>;
169-
170-
#[inline(always)]
171-
fn set_high_speed(&mut self) {
172-
self.set_speed(Speed::VeryHigh);
173-
}
174127
}
175128
impl ChipSelectPins for alt::Ne3 {
176129
type Lcds = Lcd<SubBank3>;
177-
178-
#[inline(always)]
179-
fn set_high_speed(&mut self) {
180-
self.set_speed(Speed::VeryHigh);
181-
}
182130
}
183131
impl ChipSelectPins for alt::Ne4 {
184132
type Lcds = Lcd<SubBank4>;
185-
186-
#[inline(always)]
187-
fn set_high_speed(&mut self) {
188-
self.set_speed(Speed::VeryHigh);
189-
}
190133
}
191134
chipselect! {
192135
[SubBank1, Ne1, 0], [SubBank2, Ne2, 1];
@@ -206,9 +149,7 @@ chipselect! {
206149
///
207150
/// Currently this trait is only implemented for tuples of 16 data pins. In the future,
208151
/// this driver may support 8-bit mode using 8 data pins.
209-
pub trait DataPins: sealed::Sealed {
210-
fn set_high_speed(&mut self);
211-
}
152+
pub trait DataPins: sealed::Sealed {}
212153

213154
#[allow(unused)]
214155
pub struct DataPins16 {
@@ -230,26 +171,7 @@ pub struct DataPins16 {
230171
d15: alt::D15,
231172
}
232173

233-
impl DataPins for DataPins16 {
234-
#[inline(always)]
235-
fn set_high_speed(&mut self) {
236-
self.d0.set_speed(Speed::VeryHigh);
237-
self.d1.set_speed(Speed::VeryHigh);
238-
self.d2.set_speed(Speed::VeryHigh);
239-
self.d4.set_speed(Speed::VeryHigh);
240-
self.d5.set_speed(Speed::VeryHigh);
241-
self.d6.set_speed(Speed::VeryHigh);
242-
self.d7.set_speed(Speed::VeryHigh);
243-
self.d8.set_speed(Speed::VeryHigh);
244-
self.d9.set_speed(Speed::VeryHigh);
245-
self.d10.set_speed(Speed::VeryHigh);
246-
self.d11.set_speed(Speed::VeryHigh);
247-
self.d12.set_speed(Speed::VeryHigh);
248-
self.d13.set_speed(Speed::VeryHigh);
249-
self.d14.set_speed(Speed::VeryHigh);
250-
self.d15.set_speed(Speed::VeryHigh);
251-
}
252-
}
174+
impl DataPins for DataPins16 {}
253175

254176
impl DataPins16 {
255177
#[inline(always)]
@@ -317,24 +239,17 @@ where
317239
NE: ChipSelectPins,
318240
{
319241
pub fn new(
320-
mut data: D,
321-
mut address: AD,
242+
data: D,
243+
address: AD,
322244
read_enable: impl Into<alt::Noe>,
323245
write_enable: impl Into<alt::Nwe>,
324-
mut chip_select: NE,
246+
chip_select: NE,
325247
) -> Self {
326-
data.set_high_speed();
327-
address.set_high_speed();
328-
let mut read_enable = read_enable.into();
329-
read_enable.set_speed(Speed::VeryHigh);
330-
let mut write_enable = write_enable.into();
331-
write_enable.set_speed(Speed::VeryHigh);
332-
chip_select.set_high_speed();
333248
Self {
334249
data,
335250
address,
336-
read_enable,
337-
write_enable,
251+
read_enable: read_enable.into(),
252+
write_enable: write_enable.into(),
338253
chip_select,
339254
}
340255
}

‎src/gpio/alt.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ use extipin;
6666

6767
macro_rules! pin {
6868
( $($(#[$docs:meta])* <$name:ident, $Otype:ident> for $(no: $NoPin:ident,)? [$(
69-
$(#[$attr:meta])* $PX:ident<$A:literal>,
69+
$(#[$attr:meta])* $PX:ident<$A:literal $(, Speed::$Speed:ident)?>,
7070
)*],)*) => {
7171
$(
7272
#[derive(Debug)]
@@ -143,14 +143,14 @@ macro_rules! pin {
143143
MODE: $crate::gpio::marker::NotAlt + $crate::gpio::PinMode
144144
{
145145
fn from(p: gpio::$PX<MODE>) -> Self {
146-
Self::$PX(p.into_mode())
146+
Self::$PX(p.into_mode() $(.speed($crate::gpio::Speed::$Speed))?)
147147
}
148148
}
149149

150150
$(#[$attr])*
151151
impl From<gpio::$PX<$crate::gpio::Alternate<$A, $Otype>>> for $name {
152152
fn from(p: gpio::$PX<$crate::gpio::Alternate<$A, $Otype>>) -> Self {
153-
Self::$PX(p)
153+
Self::$PX(p $(.speed($crate::gpio::Speed::$Speed))?)
154154
}
155155
}
156156

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