Merge #193

193:  Allow DMA on both halves of a split Serial<USART> separately. r=therealprof a=bobmcwhirter

Based upon and dependent upon #186

Co-authored-by: Bob McWhirter <[email protected]>

Author: bors[bot]

src/dma/traits.rs

@@ -2,6 +2,7 @@ use super::*;
 use crate::{
     bb,
     pac::{self, DMA1, DMA2, RCC},
+    serial::{Rx, Tx},
 };
 use core::ops::Deref;
 
@@ -485,19 +486,28 @@ dma_map!(
     (Stream4<DMA1>, Channel0, pac::SPI2, MemoryToPeripheral),       //SPI2_TX
     (Stream5<DMA1>, Channel1, pac::I2C1, PeripheralToMemory),       //I2C1_RX
     (Stream5<DMA1>, Channel4, pac::USART2, PeripheralToMemory),     //USART2_RX
+    (Stream5<DMA1>, Channel4, Rx<pac::USART2>, PeripheralToMemory), //USART2_RX
     (Stream6<DMA1>, Channel4, pac::USART2, MemoryToPeripheral),     //USART2_TX
+    (Stream6<DMA1>, Channel4, Tx<pac::USART2>, MemoryToPeripheral), //USART2_TX
     (Stream7<DMA1>, Channel7, pac::I2C2, MemoryToPeripheral),       //I2C2_TX
     (Stream0<DMA2>, Channel0, pac::ADC1, PeripheralToMemory),       //ADC1
     (Stream0<DMA2>, Channel3, pac::SPI1, PeripheralToMemory),       //SPI1_RX
     (Stream1<DMA2>, Channel5, pac::USART6, PeripheralToMemory),     //USART6_RX
+    (Stream1<DMA2>, Channel5, Rx<pac::USART6>, PeripheralToMemory), //USART6_RX
     (Stream2<DMA2>, Channel3, pac::SPI1, PeripheralToMemory),       //SPI1_RX
     (Stream2<DMA2>, Channel4, pac::USART1, PeripheralToMemory),     //USART1_RX
+    (Stream2<DMA2>, Channel4, Rx<pac::USART1>, PeripheralToMemory), //USART1_RX
     (Stream2<DMA2>, Channel5, pac::USART6, PeripheralToMemory),     //USART6_RX
+    (Stream2<DMA2>, Channel5, Rx<pac::USART6>, PeripheralToMemory), //USART6_RX
     (Stream4<DMA2>, Channel0, pac::ADC1, PeripheralToMemory),       //ADC1
     (Stream5<DMA2>, Channel4, pac::USART1, PeripheralToMemory),     //USART1_RX
+    (Stream5<DMA2>, Channel4, Rx<pac::USART1>, PeripheralToMemory), //USART1_RX
     (Stream6<DMA2>, Channel5, pac::USART6, MemoryToPeripheral),     //USART6_TX
+    (Stream6<DMA2>, Channel5, Tx<pac::USART6>, MemoryToPeripheral), //USART6_TX
     (Stream7<DMA2>, Channel4, pac::USART1, MemoryToPeripheral),     //USART1_TX
+    (Stream7<DMA2>, Channel4, Tx<pac::USART1>, MemoryToPeripheral), //USART1_TX
     (Stream7<DMA2>, Channel5, pac::USART6, MemoryToPeripheral),     //USART6_TX
+    (Stream7<DMA2>, Channel5, Tx<pac::USART6>, MemoryToPeripheral), //USART6_TX
     (
         Stream0<DMA2>,
         Channel0,

src/serial.rs

@@ -374,6 +374,8 @@ use crate::gpio::AF11;
 use crate::gpio::{Alternate, AF7, AF8};
 use crate::rcc::Clocks;
 
+use crate::dma::traits::PeriAddress;
+
 /// Serial error
 #[derive(Debug)]
 pub enum Error {
@@ -425,11 +427,19 @@ pub mod config {
         STOP1P5,
     }
 
+    pub enum DmaConfig {
+        None,
+        Tx,
+        Rx,
+        TxRx,
+    }
+
     pub struct Config {
         pub baudrate: Bps,
         pub wordlength: WordLength,
         pub parity: Parity,
         pub stopbits: StopBits,
+        pub dma: DmaConfig,
     }
 
     impl Config {
@@ -480,6 +490,7 @@ pub mod config {
                 wordlength: WordLength::DataBits8,
                 parity: Parity::ParityNone,
                 stopbits: StopBits::STOP1,
+                dma: DmaConfig::None,
             }
         }
     }
@@ -1442,6 +1453,27 @@ macro_rules! halUsartImpl {
                             })
                     });
 
+                    match config.dma {
+                        DmaConfig::Tx => {
+                            usart.cr3.write(|w| {
+                                w.dmat().enabled()
+                            })
+                        }
+                        DmaConfig::Rx => {
+                            usart.cr3.write(|w| {
+                                w.dmar().enabled()
+                            })
+                        }
+                        DmaConfig::TxRx => {
+                            usart.cr3.write(|w| {
+                                w
+                                    .dmar().enabled()
+                                    .dmat().enabled()
+                            })
+                        }
+                        DmaConfig::None => {}
+                    }
+
                     Ok(Serial { usart, pins }.config_stop(config))
                 }
 
@@ -1549,6 +1581,15 @@ macro_rules! halUsartImpl {
                 }
             }
 
+            unsafe impl PeriAddress for Rx<$USARTX> {
+                #[inline(always)]
+                fn address(&self) -> u32 {
+                    &(unsafe{ &(*$USARTX::ptr()) }.dr) as *const _ as u32
+                }
+
+                type MemSize = u8;
+            }
+
             impl<PINS> serial::Write<u8> for Serial<$USARTX, PINS> {
                 type Error = Error;
 
@@ -1567,6 +1608,15 @@ macro_rules! halUsartImpl {
                 }
             }
 
+            unsafe impl PeriAddress for Tx<$USARTX> {
+                #[inline(always)]
+                fn address(&self) -> u32 {
+                    &(unsafe{ &(*$USARTX::ptr()) }.dr) as *const _ as u32
+                }
+
+                type MemSize = u8;
+            }
+
             impl serial::Write<u8> for Tx<$USARTX> {
                 type Error = Error;