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Merge pull request #617 from stm32-rs/all-enums
all enums
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‎CHANGELOG.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1313
- Split USART and UART implementations [#608]
1414
- Add `lapce` editor settings [#601]
1515
- Use `enum`s for alternate peripheral pins (generic over otype) [#594] [#596] [#600] [#610]
16+
- Add missing alternate enums [#617]
1617
- Added missing U(S)ART DMA traits for HAL serial types [#593]
1718
- Improve SPI::new* docs [#587]
1819
- Add advanced timer dead time insertion example [#585]
@@ -34,6 +35,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
3435
[#609]: https://github.com/stm32-rs/stm32f4xx-hal/pull/609
3536
[#611]: https://github.com/stm32-rs/stm32f4xx-hal/pull/611
3637
[#614]: https://github.com/stm32-rs/stm32f4xx-hal/pull/614
38+
[#617]: https://github.com/stm32-rs/stm32f4xx-hal/pull/617
3739

3840
## [v0.15.0] - 2023-03-13
3941

‎Cargo.toml

Lines changed: 39 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,8 @@ gpio-f401 = [
125125
]
126126
gpio-f410 = [
127127
"dac",
128+
"fmpi2c1",
129+
"lptim1",
128130
"spi5",
129131
]
130132
gpio-f411 = [
@@ -139,8 +141,11 @@ gpio-f411 = [
139141
gpio-f412 = [
140142
"gpiod", "gpioe", "gpiof", "gpiog",
141143
"can1", "can2",
144+
"dfsdm1",
145+
"fmpi2c1",
142146
"fsmc",
143147
"i2c3",
148+
"quadspi",
144149
"otg-fs",
145150
"rng",
146151
"sdio",
@@ -152,12 +157,16 @@ gpio-f413 = [
152157
"gpiod", "gpioe", "gpiof", "gpiog",
153158
"can1", "can2", "can3",
154159
"dac",
160+
"dfsdm1",
161+
"dfsdm2",
155162
"fsmc",
156163
"fmpi2c1",
157164
"i2c3",
165+
"lptim1",
166+
"quadspi",
158167
"otg-fs",
159168
"rng",
160-
"sai",
169+
"sai1",
161170
"sdio",
162171
"spi3", "spi4", "spi5",
163172
"tim2", "tim8",
@@ -168,6 +177,8 @@ gpio-f417 = [
168177
"adc2", "adc3",
169178
"can1", "can2",
170179
"dac",
180+
"dcmi",
181+
"eth",
171182
"fsmc",
172183
"i2c3",
173184
"otg-fs",
@@ -183,11 +194,14 @@ gpio-f427 = [
183194
"adc2", "adc3",
184195
"can1", "can2",
185196
"dac",
197+
"dcmi",
198+
"eth",
186199
"i2c3",
200+
"ltdc",
187201
"otg-fs",
188202
"otg-hs",
189203
"rng",
190-
"sai",
204+
"sai1",
191205
"sdio",
192206
"spi3", "spi4", "spi5", "spi6",
193207
"tim2", "tim8",
@@ -198,13 +212,18 @@ gpio-f446 = [
198212
"adc2", "adc3",
199213
"can1", "can2",
200214
"dac",
215+
"dcmi",
216+
"fmpi2c1",
201217
"fmc",
202218
"i2c3",
219+
"quadspi",
203220
"otg-fs",
204221
"otg-hs",
205-
"sai",
222+
"sai1",
223+
"sai2",
206224
#"sdio",
207225
"spi3", "spi4",
226+
"spdifrx",
208227
"tim2", "tim8",
209228
"usart3", "uart4", "uart5",
210229
]
@@ -213,12 +232,17 @@ gpio-f469 = [
213232
"adc2", "adc3",
214233
"can1", "can2",
215234
"dac",
235+
"dcmi",
236+
"dsihost",
237+
"eth",
216238
"fmc",
217239
"i2c3",
240+
"ltdc",
241+
"quadspi",
218242
"otg-fs",
219243
"otg-hs",
220244
"rng",
221-
"sai",
245+
"sai1",
222246
"sdio",
223247
"spi3", "spi4", "spi5", "spi6",
224248
"tim2", "tim8",
@@ -242,6 +266,11 @@ can1 = []
242266
can2 = []
243267
can3 = []
244268
dac = []
269+
dcmi = []
270+
dfsdm1 = []
271+
dfsdm2 = []
272+
dsihost = []
273+
eth = []
245274
fmc = []
246275
fsmc = []
247276
fmpi2c1 = []
@@ -253,15 +282,20 @@ gpioi = []
253282
gpioj = []
254283
gpiok = []
255284
i2c3 = []
285+
lptim1 = []
286+
ltdc = []
287+
quadspi = []
256288
otg-fs = []
257289
otg-hs = []
258290
rng = []
259-
sai = []
291+
sai1 = []
292+
sai2 = []
260293
sdio = []
261294
spi3 = []
262295
spi4 = []
263296
spi5 = []
264297
spi6 = []
298+
spdifrx = []
265299
tim2 = []
266300
tim8 = []
267301
usart3 = []

‎src/can.rs

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,27 +5,21 @@ use crate::gpio::{self, NoPin};
55
use crate::pac::{CAN1, CAN2};
66
use crate::rcc;
77

8-
pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset {
9-
type Tx;
10-
type Rx;
11-
}
8+
pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + gpio::alt::CanCommon {}
129

1310
macro_rules! can {
14-
($CAN:ty: $Can:ident, $can:ident) => {
11+
($CAN:ty: $Can:ident) => {
1512
pub type $Can = Can<$CAN>;
1613

17-
impl Instance for $CAN {
18-
type Tx = gpio::alt::$can::Tx;
19-
type Rx = gpio::alt::$can::Rx;
20-
}
14+
impl Instance for $CAN {}
2115
};
2216
}
2317

2418
// Implemented by all SPI instances
25-
can! { CAN1: Can1, can1 }
26-
can! { CAN2: Can2, can2 }
19+
can! { CAN1: Can1 }
20+
can! { CAN2: Can2 }
2721
#[cfg(feature = "can3")]
28-
can! { crate::pac::CAN3: Can3, can3 }
22+
can! { crate::pac::CAN3: Can3 }
2923

3024
/// Pins and definitions for models with a third CAN peripheral
3125
#[cfg(feature = "can3")]

‎src/fmpi2c.rs

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,19 +10,14 @@ mod hal_02;
1010
mod hal_1;
1111

1212
pub trait Instance:
13-
crate::Sealed + Deref<Target = fmpi2c1::RegisterBlock> + Enable + Reset
13+
crate::Sealed + Deref<Target = fmpi2c1::RegisterBlock> + Enable + Reset + gpio::alt::I2cCommon
1414
{
15-
type Scl;
16-
type Sda;
17-
1815
#[doc(hidden)]
1916
fn ptr() -> *const fmpi2c1::RegisterBlock;
2017
fn clock_hsi(rcc: &crate::pac::rcc::RegisterBlock);
2118
}
2219

2320
impl Instance for FMPI2C1 {
24-
type Sda = gpio::alt::fmpi2c1::Sda;
25-
type Scl = gpio::alt::fmpi2c1::Scl;
2621
fn ptr() -> *const fmpi2c1::RegisterBlock {
2722
FMPI2C1::ptr() as *const _
2823
}

‎src/fsmc_lcd/pins.rs

Lines changed: 28 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -257,77 +257,62 @@ pub trait ChipSelectPins: sealed::Sealed {
257257
// 2, 3, 4
258258
// 1, 2, 3, 4
259259

260-
impl ChipSelectPins for alt::ChipSelect1 {
260+
impl ChipSelectPins for alt::Ne1 {
261261
type Lcds = Lcd<SubBank1>;
262262
}
263-
impl ChipSelectPins for alt::ChipSelect2 {
263+
impl ChipSelectPins for alt::Ne2 {
264264
type Lcds = Lcd<SubBank2>;
265265
}
266-
impl ChipSelectPins for alt::ChipSelect3 {
266+
impl ChipSelectPins for alt::Ne3 {
267267
type Lcds = Lcd<SubBank3>;
268268
}
269-
impl ChipSelectPins for alt::ChipSelect4 {
269+
impl ChipSelectPins for alt::Ne4 {
270270
type Lcds = Lcd<SubBank4>;
271271
}
272-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect2) {
272+
impl ChipSelectPins for (alt::Ne1, alt::Ne2) {
273273
type Lcds = (Lcd<SubBank1>, Lcd<SubBank2>);
274274
}
275-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect2) {}
276-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect3) {
275+
impl sealed::Sealed for (alt::Ne1, alt::Ne2) {}
276+
impl ChipSelectPins for (alt::Ne1, alt::Ne3) {
277277
type Lcds = (Lcd<SubBank1>, Lcd<SubBank3>);
278278
}
279-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect3) {}
280-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect4) {
279+
impl sealed::Sealed for (alt::Ne1, alt::Ne3) {}
280+
impl ChipSelectPins for (alt::Ne1, alt::Ne4) {
281281
type Lcds = (Lcd<SubBank1>, Lcd<SubBank4>);
282282
}
283-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect4) {}
284-
impl ChipSelectPins for (alt::ChipSelect2, alt::ChipSelect3) {
283+
impl sealed::Sealed for (alt::Ne1, alt::Ne4) {}
284+
impl ChipSelectPins for (alt::Ne2, alt::Ne3) {
285285
type Lcds = (Lcd<SubBank2>, Lcd<SubBank3>);
286286
}
287-
impl sealed::Sealed for (alt::ChipSelect2, alt::ChipSelect3) {}
288-
impl ChipSelectPins for (alt::ChipSelect2, alt::ChipSelect4) {
287+
impl sealed::Sealed for (alt::Ne2, alt::Ne3) {}
288+
impl ChipSelectPins for (alt::Ne2, alt::Ne4) {
289289
type Lcds = (Lcd<SubBank2>, Lcd<SubBank4>);
290290
}
291-
impl sealed::Sealed for (alt::ChipSelect2, alt::ChipSelect4) {}
292-
impl ChipSelectPins for (alt::ChipSelect3, alt::ChipSelect4) {
291+
impl sealed::Sealed for (alt::Ne2, alt::Ne4) {}
292+
impl ChipSelectPins for (alt::Ne3, alt::Ne4) {
293293
type Lcds = (Lcd<SubBank3>, Lcd<SubBank4>);
294294
}
295-
impl sealed::Sealed for (alt::ChipSelect3, alt::ChipSelect4) {}
296-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect2, alt::ChipSelect3) {
295+
impl sealed::Sealed for (alt::Ne3, alt::Ne4) {}
296+
impl ChipSelectPins for (alt::Ne1, alt::Ne2, alt::Ne3) {
297297
type Lcds = (Lcd<SubBank1>, Lcd<SubBank2>, Lcd<SubBank3>);
298298
}
299-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect2, alt::ChipSelect3) {}
300-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect2, alt::ChipSelect4) {
299+
impl sealed::Sealed for (alt::Ne1, alt::Ne2, alt::Ne3) {}
300+
impl ChipSelectPins for (alt::Ne1, alt::Ne2, alt::Ne4) {
301301
type Lcds = (Lcd<SubBank1>, Lcd<SubBank2>, Lcd<SubBank4>);
302302
}
303-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect2, alt::ChipSelect4) {}
304-
impl ChipSelectPins for (alt::ChipSelect1, alt::ChipSelect3, alt::ChipSelect4) {
303+
impl sealed::Sealed for (alt::Ne1, alt::Ne2, alt::Ne4) {}
304+
impl ChipSelectPins for (alt::Ne1, alt::Ne3, alt::Ne4) {
305305
type Lcds = (Lcd<SubBank1>, Lcd<SubBank3>, Lcd<SubBank4>);
306306
}
307-
impl sealed::Sealed for (alt::ChipSelect1, alt::ChipSelect3, alt::ChipSelect4) {}
308-
impl ChipSelectPins for (alt::ChipSelect2, alt::ChipSelect3, alt::ChipSelect4) {
307+
impl sealed::Sealed for (alt::Ne1, alt::Ne3, alt::Ne4) {}
308+
impl ChipSelectPins for (alt::Ne2, alt::Ne3, alt::Ne4) {
309309
type Lcds = (Lcd<SubBank2>, Lcd<SubBank3>, Lcd<SubBank4>);
310310
}
311-
impl sealed::Sealed for (alt::ChipSelect2, alt::ChipSelect3, alt::ChipSelect4) {}
312-
impl ChipSelectPins
313-
for (
314-
alt::ChipSelect1,
315-
alt::ChipSelect2,
316-
alt::ChipSelect3,
317-
alt::ChipSelect4,
318-
)
319-
{
311+
impl sealed::Sealed for (alt::Ne2, alt::Ne3, alt::Ne4) {}
312+
impl ChipSelectPins for (alt::Ne1, alt::Ne2, alt::Ne3, alt::Ne4) {
320313
type Lcds = (Lcd<SubBank1>, Lcd<SubBank2>, Lcd<SubBank3>, Lcd<SubBank4>);
321314
}
322-
impl sealed::Sealed
323-
for (
324-
alt::ChipSelect1,
325-
alt::ChipSelect2,
326-
alt::ChipSelect3,
327-
alt::ChipSelect4,
328-
)
329-
{
330-
}
315+
impl sealed::Sealed for (alt::Ne1, alt::Ne2, alt::Ne3, alt::Ne4) {}
331316

332317
/// A set of data pins
333318
///
@@ -387,9 +372,9 @@ pub struct LcdPins<D, AD, NE> {
387372
/// Address pin(s) (data/command)
388373
pub address: AD,
389374
/// Output enable (read enable)
390-
pub read_enable: alt::ReadEnable,
375+
pub read_enable: alt::Noe,
391376
/// Write enable
392-
pub write_enable: alt::WriteEnable,
377+
pub write_enable: alt::Nwe,
393378
/// Chip select / bank enable pin(s)
394379
pub chip_select: NE,
395380
}

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