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Updating error handling
1 parent bc7ce01 commit 520881e

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+65
-18
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1 file changed

+65
-18
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src/i2c.rs

Lines changed: 65 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -550,6 +550,10 @@ impl PinScl<FMPI2C> for PF15<AlternateOD<AF4>> {}
550550
pub enum Error {
551551
OVERRUN,
552552
NACK,
553+
TIMEOUT,
554+
BUS,
555+
CRC,
556+
ARBITRATION,
553557
}
554558

555559
#[cfg(any(
@@ -767,6 +771,53 @@ where
767771
self.i2c.cr1.modify(|_, w| w.pe().set_bit());
768772
}
769773

774+
fn check_and_clear_error_flags(&self) -> Result<(), Error> {
775+
let sr1 = self.i2c.sr1.read();
776+
777+
// Clear all pending error flags. We have already read the SR1, so it's safe to clear them
778+
// before returning the error code.
779+
self.i2c.sr1.modify(|_, w| {
780+
w.timeout()
781+
.clear_bit()
782+
.pecerr()
783+
.clear_bit()
784+
.ovr()
785+
.clear_bit()
786+
.af()
787+
.clear_bit()
788+
.arlo()
789+
.clear_bit()
790+
.berr()
791+
.clear_bit()
792+
});
793+
794+
if sr1.timeout().bit_is_set() {
795+
return Err(Error::TIMEOUT);
796+
}
797+
798+
if sr1.pecerr().bit_is_set() {
799+
return Err(Error::CRC);
800+
}
801+
802+
if sr1.ovr().bit_is_set() {
803+
return Err(Error::OVERRUN);
804+
}
805+
806+
if sr1.af().bit_is_set() {
807+
return Err(Error::NACK);
808+
}
809+
810+
if sr1.arlo().bit_is_set() {
811+
return Err(Error::ARBITRATION);
812+
}
813+
814+
if sr1.berr().bit_is_set() {
815+
return Err(Error::BUS);
816+
}
817+
818+
Ok(())
819+
}
820+
770821
pub fn release(self) -> (I2C, PINS) {
771822
(self.i2c, self.pins)
772823
}
@@ -804,16 +855,11 @@ where
804855

805856
// Wait until address was sent
806857
while {
807-
let sr1 = self.i2c.sr1.read();
858+
// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
859+
self.check_and_clear_error_flags()?;
808860

809-
// If we received a NACK, then this is an error
810-
if sr1.af().bit_is_set() {
811-
self.i2c.sr1.modify(|_, w| w.af().clear_bit());
812-
return Err(Error::NACK);
813-
}
814-
815-
// Wait for the address to be acknowledged.
816-
sr1.addr().bit_is_clear()
861+
// Wait for the address to be acknowledged
862+
self.i2c.sr1.read().addr().bit_is_clear()
817863
} {}
818864

819865
// Clear condition by reading SR2
@@ -837,22 +883,23 @@ where
837883

838884
// Wait until byte is transferred
839885
while {
840-
let sr1 = self.i2c.sr1.read();
841-
842-
// If we received a NACK, then this is an error
843-
if sr1.af().bit_is_set() {
844-
self.i2c.sr1.modify(|_, w| w.af().clear_bit());
845-
return Err(Error::NACK);
846-
}
886+
// Check for any potential error conditions.
887+
self.check_and_clear_error_flags()?;
847888

848-
sr1.btf().bit_is_clear()
889+
self.i2c.sr1.read().btf().bit_is_clear()
849890
} {}
850891

851892
Ok(())
852893
}
853894

854895
fn recv_byte(&self) -> Result<u8, Error> {
855-
while self.i2c.sr1.read().rx_ne().bit_is_clear() {}
896+
while {
897+
// Check for any potential error conditions.
898+
self.check_and_clear_error_flags()?;
899+
900+
self.i2c.sr1.read().rx_ne().bit_is_clear()
901+
} {}
902+
856903
let value = self.i2c.dr.read().bits() as u8;
857904
Ok(value)
858905
}

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