@@ -509,8 +509,21 @@ where
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// Send address
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self . send_address ( addr, true ) ?;
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+ // Note from STM32 RM0090:
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+ // When the number of bytes to be received is equal to or greater than two,
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+ // the DMA controller sends a hardware signal, EOT_1, corresponding to the
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+ // last but one data byte (number_of_bytes – 1). If, in the I2C_CR2 register,
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+ // the LAST bit is set, I2C automatically sends a NACK after the next byte
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+ // following EOT_1. The user can generate a Stop condition in the DMA
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+ // Transfer Complete interrupt routine if enabled.
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// On small sized array we need to set ACK=0 before ADDR cleared
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- if buf_len <= 1 {
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+ if buf_len >= 2 {
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+ self . hal_i2c . i2c . cr2 . modify ( |_, w| w. last ( ) . set_bit ( ) ) ;
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+ // When a single byte must be received: the NACK must be programmed during
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+ // EV6 event, i.e. program ACK=0 when ADDR=1, before clearing ADDR flag.
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+ // Then the user can program the STOP condition either after clearing ADDR
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+ // flag, or in the DMA Transfer Complete interrupt routine.
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+ } else {
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self . hal_i2c . i2c . cr1 . modify ( |_, w| w. ack ( ) . clear_bit ( ) ) ;
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}
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@@ -570,6 +583,7 @@ where
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fn finish_transfer_with_result ( & mut self , result : Result < ( ) , Error > ) {
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self . disable_dma_requests ( ) ;
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self . disable_error_interrupt_generation ( ) ;
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+ self . hal_i2c . i2c . cr2 . modify ( |_, w| w. last ( ) . clear_bit ( ) ) ;
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if let Err ( Error :: I2CError ( super :: Error :: NoAcknowledge ( _) ) ) = & result {
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self . send_stop ( ) ;
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