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burrbullburrbull
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update to svd2rust 0.33.3 & use stm32f4-staging
1 parent 6a8039b commit 853a500

39 files changed

+867
-887
lines changed

‎CHANGELOG.md

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
77

88
## [Unreleased]
99

10+
### Changed
11+
12+
- Use `stm32f4-staging` until `stm32f4` is released [#706]
13+
14+
[#706]: https://github.com/stm32-rs/stm32f4xx-hal/pull/706
15+
1016
## [v0.21.0] - 2024-05-30
1117

1218
### Changed

‎Cargo.toml

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@ cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
3333
cortex-m-rt = "0.7.3"
3434
nb = "1.1"
3535
rand_core = "0.6.4"
36-
stm32f4 = "0.15.1"
3736
synopsys-usb-otg = { version = "0.4.0", features = [
3837
"cortex-m",
3938
], optional = true }
@@ -62,6 +61,11 @@ embedded-storage = "0.3"
6261
vcell = "0.1.3"
6362
document-features = "0.2"
6463

64+
[dependencies.stm32f4]
65+
package = "stm32f4-staging"
66+
version = "0.16.0"
67+
features = ["defmt", "atomics"]
68+
6569
[dependencies.time]
6670
version = "0.3.14"
6771
default-features = false

‎examples/analog-stopwatch-with-spi-ssd1306.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ enum StopwatchState {
6565
fn main() -> ! {
6666
let mut dp = pac::Peripherals::take().unwrap();
6767
let cp = cortex_m::peripheral::Peripherals::take().unwrap();
68-
dp.RCC.apb2enr.write(|w| w.syscfgen().enabled());
68+
dp.RCC.apb2enr().write(|w| w.syscfgen().enabled());
6969

7070
let rcc = dp.RCC.constrain();
7171

‎src/adc.rs

Lines changed: 55 additions & 55 deletions
Large diffs are not rendered by default.

‎src/crc32.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ impl Crc32 {
3535
/// Reset the internal CRC32 state to the default value (0xFFFF_FFFF)
3636
#[inline(always)]
3737
pub fn init(&mut self) {
38-
self.periph.cr.write(|w| w.reset().reset());
38+
self.periph.cr().write(|w| w.reset().reset());
3939
}
4040

4141
/// Feed words into the CRC engine.
@@ -45,10 +45,10 @@ impl Crc32 {
4545
pub fn update(&mut self, data: &[u32]) -> u32 {
4646
// Feed each word into the engine
4747
for word in data {
48-
self.periph.dr.write(|w| w.bits(*word));
48+
self.periph.dr().write(|w| w.set(*word));
4949
}
5050
// Retrieve the resulting CRC
51-
self.periph.dr.read().bits()
51+
self.periph.dr().read().bits()
5252
}
5353

5454
/// Feed bytes into the CRC engine.
@@ -95,7 +95,7 @@ impl Crc32 {
9595
// Mark the scratch bytes as initialized, and then convert it to a
9696
// native-endian u32. Feed this into the CRC peripheral
9797
self.periph
98-
.dr
98+
.dr()
9999
.write(|w| w.bits(u32::from_ne_bytes(scratch.assume_init())));
100100
});
101101

@@ -109,11 +109,11 @@ impl Crc32 {
109109
// MOST significant bytes as zeroes
110110
scratch[..remainder.len()].copy_from_slice(remainder);
111111
self.periph
112-
.dr
113-
.write(|w| w.bits(u32::from_ne_bytes(scratch)));
112+
.dr()
113+
.write(|w| w.set(u32::from_ne_bytes(scratch)));
114114
}
115115

116-
self.periph.dr.read().bits()
116+
self.periph.dr().read().bits()
117117
}
118118

119119
/// Consume the HAL peripheral, returning the PAC peripheral

‎src/dac.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,19 +67,19 @@ macro_rules! dac {
6767
impl DacPin for $CX {
6868
fn enable(&mut self) {
6969
let dac = unsafe { &(*DAC::ptr()) };
70-
dac.cr.modify(|_, w| w.$en().set_bit());
70+
dac.cr().modify(|_, w| w.$en().set_bit());
7171
}
7272
}
7373

7474
impl DacOut<u16> for $CX {
7575
fn set_value(&mut self, val: u16) {
7676
let dac = unsafe { &(*DAC::ptr()) };
77-
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
77+
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
7878
}
7979

8080
fn get_value(&mut self) -> u16 {
8181
let dac = unsafe { &(*DAC::ptr()) };
82-
dac.$dac_dor.read().bits() as u16
82+
dac.$dac_dor().read().bits() as u16
8383
}
8484
}
8585
};
@@ -101,4 +101,5 @@ impl DacExt for DAC {
101101
}
102102

103103
dac!(C1, en1, cen1, cal_flag1, otrim1, mode1, dhr12r1, dor1, dacc1dhr);
104+
#[cfg(not(feature = "stm32f410"))]
104105
dac!(C2, en2, cen2, cal_flag2, otrim2, mode2, dhr12r2, dor2, dacc2dhr);

‎src/dma/mod.rs

Lines changed: 44 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -383,12 +383,12 @@ impl<DMA: Instance, const S: u8> StreamX<DMA, S> {
383383
#[cfg(not(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410")))]
384384
#[inline(always)]
385385
unsafe fn st() -> &'static pac::dma2::ST {
386-
&(*DMA::ptr()).st[S as usize]
386+
(*DMA::ptr()).st(S as usize)
387387
}
388388
#[cfg(any(feature = "gpio-f411", feature = "gpio-f413", feature = "gpio-f410"))]
389389
#[inline(always)]
390390
unsafe fn st() -> &'static pac::dma1::ST {
391-
&(*DMA::ptr()).st[S as usize]
391+
(*DMA::ptr()).st(S as usize)
392392
}
393393
}
394394

@@ -481,183 +481,187 @@ where
481481
#[inline(always)]
482482
fn set_peripheral_address(&mut self, value: u32) {
483483
unsafe { Self::st() }
484-
.par
484+
.par()
485485
.write(|w| unsafe { w.pa().bits(value) });
486486
}
487487

488488
#[inline(always)]
489489
fn set_memory_address(&mut self, value: u32) {
490490
unsafe { Self::st() }
491-
.m0ar
491+
.m0ar()
492492
.write(|w| unsafe { w.m0a().bits(value) });
493493
}
494494

495495
#[inline(always)]
496496
fn memory_address(&self) -> u32 {
497-
unsafe { Self::st() }.m0ar.read().m0a().bits()
497+
unsafe { Self::st() }.m0ar().read().m0a().bits()
498498
}
499499

500500
#[inline(always)]
501501
fn set_alternate_memory_address(&mut self, value: u32) {
502502
unsafe { Self::st() }
503-
.m1ar
503+
.m1ar()
504504
.write(|w| unsafe { w.m1a().bits(value) });
505505
}
506506

507507
#[inline(always)]
508508
fn alternate_memory_address(&self) -> u32 {
509-
unsafe { Self::st() }.m1ar.read().m1a().bits()
509+
unsafe { Self::st() }.m1ar().read().m1a().bits()
510510
}
511511

512512
#[inline(always)]
513513
fn set_number_of_transfers(&mut self, value: u16) {
514-
unsafe { Self::st() }.ndtr.write(|w| w.ndt().bits(value));
514+
unsafe { Self::st() }.ndtr().write(|w| w.ndt().set(value));
515515
}
516516

517517
#[inline(always)]
518518
fn number_of_transfers(&self) -> u16 {
519-
unsafe { Self::st() }.ndtr.read().ndt().bits()
519+
unsafe { Self::st() }.ndtr().read().ndt().bits()
520520
}
521521

522522
#[inline(always)]
523523
unsafe fn enable(&mut self) {
524-
Self::st().cr.modify(|_, w| w.en().set_bit());
524+
Self::st().cr().modify(|_, w| w.en().set_bit());
525525
}
526526

527527
#[inline(always)]
528528
fn is_enabled(&self) -> bool {
529-
unsafe { Self::st() }.cr.read().en().bit_is_set()
529+
unsafe { Self::st() }.cr().read().en().bit_is_set()
530530
}
531531

532532
#[inline(always)]
533533
unsafe fn disable(&mut self) {
534-
unsafe { Self::st() }.cr.modify(|_, w| w.en().clear_bit());
534+
unsafe { Self::st() }.cr().modify(|_, w| w.en().clear_bit());
535535
}
536536

537537
#[inline(always)]
538538
fn set_channel(&mut self, channel: DmaChannel) {
539539
unsafe { Self::st() }
540-
.cr
541-
.modify(|_, w| w.chsel().bits(channel.bits()));
540+
.cr()
541+
.modify(|_, w| w.chsel().set(channel.bits()));
542542
}
543543

544544
#[inline(always)]
545545
fn set_priority(&mut self, priority: config::Priority) {
546546
unsafe { Self::st() }
547-
.cr
548-
.modify(|_, w| w.pl().bits(priority.bits()));
547+
.cr()
548+
.modify(|_, w| w.pl().set(priority.bits()));
549549
}
550550

551551
#[inline(always)]
552552
fn set_peripheral_increment_offset(&mut self, value: PeripheralIncrementOffset) {
553553
unsafe { Self::st() }
554-
.cr
554+
.cr()
555555
.modify(|_, w| w.pincos().bit(value.bits()));
556556
}
557557

558558
#[inline(always)]
559559
unsafe fn set_memory_size(&mut self, size: DmaDataSize) {
560-
Self::st().cr.modify(|_, w| w.msize().bits(size.bits()));
560+
Self::st().cr().modify(|_, w| w.msize().bits(size.bits()));
561561
}
562562

563563
#[inline(always)]
564564
unsafe fn set_peripheral_size(&mut self, size: DmaDataSize) {
565-
Self::st().cr.modify(|_, w| w.psize().bits(size.bits()));
565+
Self::st().cr().modify(|_, w| w.psize().bits(size.bits()));
566566
}
567567

568568
#[inline(always)]
569569
fn set_memory_increment(&mut self, increment: bool) {
570570
unsafe { Self::st() }
571-
.cr
571+
.cr()
572572
.modify(|_, w| w.minc().bit(increment));
573573
}
574574

575575
#[inline(always)]
576576
fn set_peripheral_increment(&mut self, increment: bool) {
577577
unsafe { Self::st() }
578-
.cr
578+
.cr()
579579
.modify(|_, w| w.pinc().bit(increment));
580580
}
581581

582582
#[inline(always)]
583583
fn set_circular_mode(&mut self, value: bool) {
584-
unsafe { Self::st() }.cr.modify(|_, w| w.circ().bit(value));
584+
unsafe { Self::st() }
585+
.cr()
586+
.modify(|_, w| w.circ().bit(value));
585587
}
586588

587589
#[inline(always)]
588590
fn set_direction(&mut self, direction: DmaDirection) {
589591
unsafe { Self::st() }
590-
.cr
592+
.cr()
591593
.modify(|_, w| unsafe { w.dir().bits(direction.bits()) });
592594
}
593595

594596
#[inline(always)]
595597
fn set_flow_controller(&mut self, value: DmaFlowController) {
596598
unsafe { Self::st() }
597-
.cr
599+
.cr()
598600
.modify(|_, w| w.pfctrl().bit(value.bits()));
599601
}
600602

601603
#[inline(always)]
602604
fn events(&self) -> BitFlags<DmaEvent> {
603-
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits())
605+
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr().read().bits())
604606
}
605607

606608
#[inline(always)]
607609
fn listen_fifo_error(&mut self) {
608-
unsafe { Self::st() }.fcr.modify(|_, w| w.feie().set_bit());
610+
unsafe { Self::st() }
611+
.fcr()
612+
.modify(|_, w| w.feie().set_bit());
609613
}
610614

611615
#[inline(always)]
612616
fn unlisten_fifo_error(&mut self) {
613617
unsafe { Self::st() }
614-
.fcr
618+
.fcr()
615619
.modify(|_, w| w.feie().clear_bit());
616620
}
617621

618622
#[inline(always)]
619623
fn set_double_buffer(&mut self, double_buffer: bool) {
620624
unsafe { Self::st() }
621-
.cr
625+
.cr()
622626
.modify(|_, w| w.dbm().bit(double_buffer));
623627
}
624628

625629
#[inline(always)]
626630
fn set_fifo_threshold(&mut self, fifo_threshold: config::FifoThreshold) {
627631
unsafe { Self::st() }
628-
.fcr
629-
.modify(|_, w| w.fth().bits(fifo_threshold.bits()));
632+
.fcr()
633+
.modify(|_, w| w.fth().set(fifo_threshold.bits()));
630634
}
631635

632636
#[inline(always)]
633637
fn set_fifo_enable(&mut self, fifo_enable: bool) {
634638
//Register is actually direct mode disable rather than fifo enable
635639
unsafe { Self::st() }
636-
.fcr
640+
.fcr()
637641
.modify(|_, w| w.dmdis().bit(fifo_enable));
638642
}
639643

640644
#[inline(always)]
641645
fn set_memory_burst(&mut self, memory_burst: config::BurstMode) {
642646
unsafe { Self::st() }
643-
.cr
644-
.modify(|_, w| w.mburst().bits(memory_burst.bits()));
647+
.cr()
648+
.modify(|_, w| w.mburst().set(memory_burst.bits()));
645649
}
646650

647651
#[inline(always)]
648652
fn set_peripheral_burst(&mut self, peripheral_burst: config::BurstMode) {
649653
unsafe { Self::st() }
650-
.cr
651-
.modify(|_, w| w.pburst().bits(peripheral_burst.bits()));
654+
.cr()
655+
.modify(|_, w| w.pburst().set(peripheral_burst.bits()));
652656
}
653657

654658
#[inline(always)]
655659
fn fifo_level(&self) -> FifoLevel {
656-
unsafe { Self::st() }.fcr.read().fs().bits().into()
660+
unsafe { Self::st() }.fcr().read().fs().bits().into()
657661
}
658662

659663
fn current_buffer(&self) -> CurrentBuffer {
660-
if unsafe { Self::st() }.cr.read().ct().bit_is_set() {
664+
if unsafe { Self::st() }.cr().read().ct().bit_is_set() {
661665
CurrentBuffer::SecondBuffer
662666
} else {
663667
CurrentBuffer::FirstBuffer
@@ -675,7 +679,7 @@ where
675679
enable: Option<BitFlags<DmaEvent>>,
676680
) {
677681
unsafe {
678-
Self::st().cr.modify(|r, w| {
682+
Self::st().cr().modify(|r, w| {
679683
w.bits({
680684
let mut bits = r.bits();
681685
if let Some(d) = disable {
@@ -704,7 +708,7 @@ macro_rules! dma_stream {
704708
#[inline(always)]
705709
fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>) {
706710
let dma = unsafe { &*I::ptr() };
707-
dma.$ifcr.write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
711+
dma.$ifcr().write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
708712
}
709713
}
710714

@@ -717,7 +721,7 @@ macro_rules! dma_stream {
717721
//NOTE(unsafe) Atomic read with no side effects
718722
let dma = unsafe { &*I::ptr() };
719723
BitFlags::from_bits_truncate(
720-
((dma.$isr.read().bits() >> $isr_shift))
724+
((dma.$isr().read().bits() >> $isr_shift))
721725
)
722726
}
723727
}

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