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move pins after
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‎CHANGELOG.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
2424

2525
- RTC: `ClockSource` enum instead of generic [#785]
2626
- Bump MSRV to 1.62 [#778]
27+
- Move PWM pins connecting after PWM inialization [#791]
2728
- Use `stm32f4-staging` until `stm32f4` is released [#706]
2829
- use GPIO pac fields instead of raw write [#777]
2930
- RTIC2 monotonics fix: CC1 instead of CC3 [#771]
@@ -51,6 +52,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
5152
[#778]: https://github.com/stm32-rs/stm32f4xx-hal/pull/778
5253
[#783]: https://github.com/stm32-rs/stm32f4xx-hal/pull/783
5354
[#785]: https://github.com/stm32-rs/stm32f4xx-hal/pull/785
55+
[#791]: https://github.com/stm32-rs/stm32f4xx-hal/pull/791
5456
[#796]: https://github.com/stm32-rs/stm32f4xx-hal/pull/796
5557

5658
## [v0.21.0] - 2024-05-30

‎examples/pwm-dead-time.rs‎

Lines changed: 10 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,7 @@ use panic_halt as _; // panic handler
99
use cortex_m_rt::entry;
1010
use stm32f4xx_hal as hal;
1111

12-
use hal::{
13-
pac,
14-
prelude::*,
15-
timer::Channel,
16-
timer::{Channel1, Polarity},
17-
};
12+
use hal::{pac, prelude::*, timer::Polarity};
1813

1914
#[entry]
2015
fn main() -> ! {
@@ -25,21 +20,21 @@ fn main() -> ! {
2520

2621
let gpioa = dp.GPIOA.split();
2722

28-
let channels = Channel1::new(gpioa.pa8).with_complementary(gpioa.pa7);
23+
let (mut pwm_mngr, (pwm_c1, ..)) = dp.TIM1.pwm_hz(20.kHz(), &clocks);
2924

30-
let mut pwm = dp.TIM1.pwm_hz(channels, 20.kHz(), &clocks);
25+
let mut pwm_c1 = pwm_c1.with(gpioa.pa8).with_complementary(gpioa.pa7);
3126

32-
let max_duty: u16 = pwm.get_max_duty();
27+
let max_duty: u16 = pwm_c1.get_max_duty();
3328

34-
pwm.set_polarity(Channel::C1, Polarity::ActiveHigh);
35-
pwm.set_complementary_polarity(Channel::C1, Polarity::ActiveHigh);
29+
pwm_c1.set_polarity(Polarity::ActiveHigh);
30+
pwm_c1.set_complementary_polarity(Polarity::ActiveHigh);
3631

37-
pwm.set_duty(Channel::C1, max_duty / 2);
32+
pwm_c1.set_duty(max_duty / 2);
3833

39-
pwm.set_dead_time(200);
34+
pwm_mngr.set_dead_time(200);
4035

41-
pwm.enable(Channel::C1);
42-
pwm.enable_complementary(Channel::C1);
36+
pwm_c1.enable();
37+
pwm_c1.enable_complementary();
4338
}
4439

4540
loop {

‎examples/pwm-input.rs‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,7 @@
66
use panic_halt as _;
77

88
use cortex_m_rt::entry;
9-
use stm32f4xx_hal::{
10-
pac,
11-
prelude::*,
12-
timer::{Channel1, Channel2, Timer},
13-
};
9+
use stm32f4xx_hal::{pac, prelude::*, timer::Timer};
1410

1511
#[entry]
1612
fn main() -> ! {
@@ -22,10 +18,10 @@ fn main() -> ! {
2218
let gpioa = dp.GPIOA.split();
2319
let gpioc = dp.GPIOC.split();
2420

25-
let channels = (Channel1::new(gpioa.pa8), Channel2::new(gpioa.pa9));
2621
// configure tim1 as a PWM output of known frequency.
27-
let pwm = Timer::new(dp.TIM1, &clocks).pwm_hz(channels, 501.Hz());
28-
let (mut ch1, _ch2) = pwm.split();
22+
let (_, (ch1, ch2, ..)) = Timer::new(dp.TIM1, &clocks).pwm_hz(501.Hz());
23+
let mut ch1 = ch1.with(gpioa.pa8);
24+
let mut _ch2 = ch2.with(gpioa.pa9);
2925
let max_duty = ch1.get_max_duty();
3026
ch1.set_duty(max_duty / 2);
3127
ch1.enable();

‎examples/pwm-sinus.rs‎

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8,11 +8,7 @@ use panic_halt as _;
88
use core::f32::consts::FRAC_PI_2;
99
use cortex_m_rt::entry;
1010
use micromath::F32Ext;
11-
use stm32f4xx_hal::{
12-
pac,
13-
prelude::*,
14-
timer::{Channel, Channel1, Channel2},
15-
};
11+
use stm32f4xx_hal::{pac, prelude::*};
1612

1713
#[entry]
1814
fn main() -> ! {
@@ -22,11 +18,13 @@ fn main() -> ! {
2218
let clocks = rcc.cfgr.use_hse(25.MHz()).freeze();
2319

2420
let gpioa = dp.GPIOA.split();
25-
let channels = (Channel1::new(gpioa.pa8), Channel2::new(gpioa.pa9));
2621

27-
let mut pwm = dp.TIM1.pwm_us(channels, 100.micros(), &clocks);
22+
let (_, (pwm_c1, pwm_c2, ..)) = dp.TIM1.pwm_us(100.micros(), &clocks);
23+
let mut pwm_c1 = pwm_c1.with(gpioa.pa8);
24+
let mut pwm_c2 = pwm_c2.with(gpioa.pa9);
25+
2826
let mut counter = dp.TIM2.counter_us(&clocks);
29-
let max_duty = pwm.get_max_duty();
27+
let max_duty = pwm_c1.get_max_duty();
3028

3129
const N: usize = 50;
3230
let mut sin_a = [0_u16; N + 1];
@@ -38,24 +36,24 @@ fn main() -> ! {
3836
}
3937

4038
counter.start(100.micros()).unwrap();
41-
pwm.enable(Channel::C1);
42-
pwm.enable(Channel::C2);
39+
pwm_c1.enable();
40+
pwm_c2.enable();
4341
let mut i = 0;
4442
loop {
4543
if i == 0 {
46-
pwm.set_duty(Channel::C2, 0);
44+
pwm_c2.set_duty(0);
4745
}
4846
if i == 2 * N {
49-
pwm.set_duty(Channel::C1, 0);
47+
pwm_c1.set_duty(0);
5048
}
5149
if i < N {
52-
pwm.set_duty(Channel::C1, sin_a[i]);
50+
pwm_c1.set_duty(sin_a[i]);
5351
} else if i < 2 * N {
54-
pwm.set_duty(Channel::C1, sin_a[2 * N - i]);
52+
pwm_c1.set_duty(sin_a[2 * N - i]);
5553
} else if i < 3 * N {
56-
pwm.set_duty(Channel::C2, sin_a[i - 2 * N]);
54+
pwm_c2.set_duty(sin_a[i - 2 * N]);
5755
} else {
58-
pwm.set_duty(Channel::C2, sin_a[4 * N - i]);
56+
pwm_c2.set_duty(sin_a[4 * N - i]);
5957
}
6058
nb::block!(counter.wait()).unwrap();
6159
i += 1;

‎examples/pwm.rs‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,7 @@
66
use panic_halt as _;
77

88
use cortex_m_rt::entry;
9-
use stm32f4xx_hal::{
10-
pac,
11-
prelude::*,
12-
timer::{Channel1, Channel2},
13-
};
9+
use stm32f4xx_hal::{pac, prelude::*};
1410

1511
#[entry]
1612
fn main() -> ! {
@@ -20,10 +16,11 @@ fn main() -> ! {
2016
let clocks = rcc.cfgr.freeze();
2117

2218
let gpioa = dp.GPIOA.split();
23-
let channels = (Channel1::new(gpioa.pa8), Channel2::new(gpioa.pa9));
2419

25-
let pwm = dp.TIM1.pwm_hz(channels, 20.kHz(), &clocks).split();
26-
let (mut ch1, _ch2) = pwm;
20+
let (_, (ch1, ch2, ..)) = dp.TIM1.pwm_us(100.micros(), &clocks);
21+
let mut ch1 = ch1.with(gpioa.pa8);
22+
let mut _ch2 = ch2.with(gpioa.pa9);
23+
2724
let max_duty = ch1.get_max_duty();
2825
ch1.set_duty(max_duty / 2);
2926
ch1.enable();

‎src/timer.rs‎

Lines changed: 58 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -317,7 +317,7 @@ pub type CCR4<T> = CCR<T, 3>;
317317
pub struct DMAR<T>(T);
318318

319319
mod sealed {
320-
use super::{BitFlags, Channel, Event, Flag, IdleState, Ocm, Polarity};
320+
use super::{BitFlags, Event, Flag, IdleState, Ocm, Polarity};
321321
pub trait General {
322322
type Width: Into<u32> + From<u16>;
323323
fn max_auto_reload() -> u32;
@@ -364,14 +364,20 @@ mod sealed {
364364
}
365365

366366
pub trait WithPwm: WithPwmCommon {
367-
fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: Ocm);
367+
fn preload_output_channel_in_mode(&mut self, c: u8, mode: Ocm);
368+
fn freeze_output_channel(&mut self, c: u8);
368369
fn start_pwm(&mut self);
369370
}
370371

371372
pub trait MasterTimer: General {
372373
type Mms;
373374
fn master_mode(&mut self, mode: Self::Mms);
374375
}
376+
377+
pub trait Split {
378+
type Channels;
379+
fn split() -> Self::Channels;
380+
}
375381
}
376382
pub(crate) use sealed::{Advanced, General, MasterTimer, WithPwm, WithPwmCommon};
377383

@@ -380,6 +386,27 @@ pub trait Instance:
380386
{
381387
}
382388

389+
use sealed::Split;
390+
macro_rules! split {
391+
($TIM:ty: 1) => {
392+
split!($TIM, C1);
393+
};
394+
($TIM:ty: 2) => {
395+
split!($TIM, C1, C2);
396+
};
397+
($TIM:ty: 4) => {
398+
split!($TIM, C1, C2, C3, C4);
399+
};
400+
($TIM:ty, $($C:ident),+) => {
401+
impl Split for $TIM {
402+
type Channels = ($(PwmChannelDisabled<$TIM, $C>,)+);
403+
fn split() -> Self::Channels {
404+
($(PwmChannelDisabled::<_, $C>::new(),)+)
405+
}
406+
}
407+
};
408+
}
409+
383410
macro_rules! hal {
384411
($TIM:ty: [
385412
$Timer:ident,
@@ -389,6 +416,11 @@ macro_rules! hal {
389416
$(m: $timbase:ident,)?
390417
]) => {
391418
impl Instance for $TIM { }
419+
impl crate::Steal for $TIM {
420+
unsafe fn steal() -> Self {
421+
Self::steal()
422+
}
423+
}
392424
pub type $Timer = Timer<$TIM>;
393425

394426
impl General for $TIM {
@@ -577,6 +609,7 @@ macro_rules! hal {
577609
)?
578610

579611
with_pwm!($TIM: $cnum $(, $aoe)?);
612+
split!($TIM: $cnum);
580613
unsafe impl<const C: u8> PeriAddress for CCR<$TIM, C> {
581614
#[inline(always)]
582615
fn address(&self) -> u32 {
@@ -611,13 +644,13 @@ macro_rules! with_dmar {
611644
}
612645

613646
macro_rules! with_pwm {
614-
($TIM:ty: [$($Cx:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident;)+] $(, $aoe:ident)?) => {
647+
($TIM:ty: [$($Cx:literal, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident;)+] $(, $aoe:ident)?) => {
615648
impl WithPwm for $TIM {
616649
#[inline(always)]
617-
fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: Ocm) {
618-
match channel {
650+
fn preload_output_channel_in_mode(&mut self, c: u8, mode: Ocm) {
651+
match c {
619652
$(
620-
Channel::$Cx => {
653+
$Cx => {
621654
self.$ccmrx_output()
622655
.modify(|_, w| w.$ocxpe().set_bit().$ocxm().set(mode as _) );
623656
}
@@ -626,6 +659,18 @@ macro_rules! with_pwm {
626659
_ => {},
627660
}
628661
}
662+
fn freeze_output_channel(&mut self, c: u8) {
663+
match c {
664+
$(
665+
$Cx => {
666+
self.$ccmrx_output()
667+
.modify(|_, w| w.$ocxpe().clear_bit().$ocxm().set(Ocm::Frozen as _) );
668+
}
669+
)+
670+
#[allow(unreachable_patterns)]
671+
_ => {},
672+
}
673+
}
629674

630675
#[inline(always)]
631676
fn start_pwm(&mut self) {
@@ -636,21 +681,21 @@ macro_rules! with_pwm {
636681
};
637682
($TIM:ty: 1) => {
638683
with_pwm!($TIM: [
639-
C1, ccmr1_output, oc1pe, oc1m;
684+
0, ccmr1_output, oc1pe, oc1m;
640685
]);
641686
};
642687
($TIM:ty: 2) => {
643688
with_pwm!($TIM: [
644-
C1, ccmr1_output, oc1pe, oc1m;
645-
C2, ccmr1_output, oc2pe, oc2m;
689+
0, ccmr1_output, oc1pe, oc1m;
690+
1, ccmr1_output, oc2pe, oc2m;
646691
]);
647692
};
648693
($TIM:ty: 4 $(, $aoe:ident)?) => {
649694
with_pwm!($TIM: [
650-
C1, ccmr1_output, oc1pe, oc1m;
651-
C2, ccmr1_output, oc2pe, oc2m;
652-
C3, ccmr2_output, oc3pe, oc3m;
653-
C4, ccmr2_output, oc4pe, oc4m;
695+
0, ccmr1_output, oc1pe, oc1m;
696+
1, ccmr1_output, oc2pe, oc2m;
697+
2, ccmr2_output, oc3pe, oc3m;
698+
3, ccmr2_output, oc4pe, oc4m;
654699
] $(, $aoe)?);
655700
};
656701
}

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