QeiExt

Author: burrbull

CHANGELOG.md

@@ -22,7 +22,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use fugit rate types instead of custom [#430]
 - Add channel events, make Event use bitflags (simplify interrupt handling) [#425]
 - reexport `digital::v2::PinState` again [#428]
-- Timer impls with time based on `fugit` moved to `fugit` module, added `Pwm` and `fugit-timer` impls [#423]
+- Timer impls with time based on `fugit::Duration` same as `Hertz` moved to `timer` module,
+  added appropriate `Ext` traits implemented on peripherals directly,
+  added `Pwm` and `fugit-timer` impls [#423] [#449]
 
 ### Fixed
 
@@ -60,6 +62,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#430]: https://github.com/stm32-rs/stm32f4xx-hal/pull/430
 [#447]: https://github.com/stm32-rs/stm32f4xx-hal/pull/447
 [#448]: https://github.com/stm32-rs/stm32f4xx-hal/pull/448
+[#449]: https://github.com/stm32-rs/stm32f4xx-hal/pull/449
 
 ### Changed
 

examples/qei.rs

@@ -14,7 +14,7 @@ use panic_halt as _;
 
 use cortex_m_rt::entry;
 use embedded_hal::Direction as RotaryDirection;
-use stm32f4xx_hal::{pac, prelude::*, qei::Qei, timer::Timer};
+use stm32f4xx_hal::{pac, prelude::*, qei::Qei};
 
 #[entry]
 fn main() -> ! {
@@ -31,7 +31,7 @@ fn main() -> ! {
     let clocks = rcc.cfgr.freeze();
 
     // Create a delay abstraction based on SysTick.
-    let mut delay = Timer::syst(cp.SYST, &clocks).delay();
+    let mut delay = cp.SYST.delay(&clocks);
 
     let gpioa = dp.GPIOA.split();
 

examples/serial-9bit.rs

@@ -34,7 +34,7 @@ use panic_halt as _;
 use cortex_m_rt::entry;
 use stm32f4xx_hal as hal;
 
-use crate::hal::{block, pac, prelude::*, serial::config::Config, timer::Timer};
+use crate::hal::{block, pac, prelude::*, serial::config::Config};
 
 use core::ops::Range;
 
@@ -55,7 +55,7 @@ fn main() -> ! {
 
     let clocks = rcc.cfgr.use_hse(8.MHz()).freeze();
 
-    let mut delay = Timer::syst(cp.SYST, &clocks).delay();
+    let mut delay = cp.SYST.delay(&clocks);
 
     // define RX/TX pins
     let tx_pin = gpioa.pa2.into_alternate();

src/prelude.rs

@@ -64,6 +64,7 @@ pub use crate::gpio::ExtiPin as _stm32f4xx_hal_gpio_ExtiPin;
 pub use crate::gpio::GpioExt as _stm32f4xx_hal_gpio_GpioExt;
 pub use crate::i2c::I2cExt as _stm32f4xx_hal_i2c_I2cExt;
 pub use crate::i2s::I2sExt as _stm32f4xx_hal_i2s_I2sExt;
+pub use crate::qei::QeiExt as _stm32f4xx_hal_QeiExt;
 pub use crate::rcc::RccExt as _stm32f4xx_hal_rcc_RccExt;
 #[cfg(all(feature = "device-selected", feature = "rng"))]
 pub use crate::rng::RngExt as _stm32f4xx_hal_rng_RngExt;

src/qei.rs

@@ -4,6 +4,20 @@ use crate::{pac::RCC, rcc, timer::General};
 pub trait Pins<TIM> {}
 use crate::timer::CPin;
 
+pub trait QeiExt<PINS>: Sized {
+    fn qei(self, pins: PINS) -> Qei<Self, PINS>;
+}
+
+impl<TIM, PINS> QeiExt<PINS> for TIM
+where
+    TIM: Instance,
+    PINS: Pins<TIM>,
+{
+    fn qei(self, pins: PINS) -> Qei<Self, PINS> {
+        Qei::new(self, pins)
+    }
+}
+
 impl<TIM, PC1, PC2> Pins<TIM> for (PC1, PC2)
 where
     PC1: CPin<TIM, 0>,
@@ -17,13 +31,12 @@ pub struct Qei<TIM, PINS> {
     pins: PINS,
 }
 
-impl<TIM: Instance, PC1, PC2> Qei<TIM, (PC1, PC2)>
+impl<TIM: Instance, PINS> Qei<TIM, PINS>
 where
-    PC1: CPin<TIM, 0>,
-    PC2: CPin<TIM, 1>,
+    PINS: Pins<TIM>,
 {
     /// Configures a TIM peripheral as a quadrature encoder interface input
-    pub fn new(mut tim: TIM, pins: (PC1, PC2)) -> Self {
+    pub fn new(mut tim: TIM, pins: PINS) -> Self {
         // NOTE(unsafe) this reference will only be used for atomic writes with no side effects.
         let rcc = unsafe { &(*RCC::ptr()) };
         // Enable and reset clock.

src/timer.rs

@@ -26,6 +26,7 @@ pub mod pwm;
 pub use pwm::*;
 #[cfg(not(feature = "stm32f410"))]
 pub mod pwm_input;
+#[cfg(not(feature = "stm32f410"))]
 pub use pwm_input::PwmInput;
 #[cfg(feature = "rtic")]
 #[cfg(not(feature = "stm32f410"))]