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fix compile on nightly
1 parent b6b7011 commit b120fc8

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3 files changed

+6
-4
lines changed

3 files changed

+6
-4
lines changed

Cargo.toml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ rtic-monotonic = { version = "1.0", optional = true }
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systick-monotonic = { version = "1.0", optional = true }
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bitflags = "2.2"
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embedded-storage = "0.2"
51+
vcell = "0.1.3"
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[dependencies.time]
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version = "0.3.14"

src/spi.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
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use core::marker::PhantomData;
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use core::ops::{Deref, DerefMut};
3-
use core::ptr;
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54
use crate::dma::traits::{DMASet, PeriAddress};
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use crate::dma::{MemoryToPeripheral, PeripheralToMemory};
@@ -739,12 +738,14 @@ impl<SPI: Instance> Inner<SPI> {
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fn read_data_reg<W: FrameSize>(&mut self) -> W {
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// NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
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// reading a half-word)
742-
unsafe { ptr::read_volatile(&self.spi.dr as *const _ as *const W) }
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unsafe { (*(&self.spi.dr as *const pac::spi1::DR).cast::<vcell::VolatileCell<W>>()).get() }
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}
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fn write_data_reg<W: FrameSize>(&mut self, data: W) {
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// NOTE(write_volatile) see note above
747-
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut W, data) }
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unsafe {
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(*(&self.spi.dr as *const pac::spi1::DR).cast::<vcell::VolatileCell<W>>()).set(data)
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}
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}
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#[inline(always)]

src/watchdog.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ impl IndependentWatchdog {
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fn setup(&self, timeout_ms: MilliSeconds) {
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assert!(timeout_ms.ticks() < (1 << 15), "Watchdog timeout to high");
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let pr = match timeout_ms.ticks() {
49-
t if t == 0 => 0b000, // <= (MAX_PR + 1) * 4 / LSI_KHZ => 0b000,
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0 => 0b000, // <= (MAX_PR + 1) * 4 / LSI_KHZ => 0b000,
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t if t <= (MAX_PR + 1) * 8 / LSI_KHZ => 0b001,
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t if t <= (MAX_PR + 1) * 16 / LSI_KHZ => 0b010,
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t if t <= (MAX_PR + 1) * 32 / LSI_KHZ => 0b011,

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