ff

Author: burrbull

Cargo.toml

@@ -264,9 +264,6 @@ gpio-f411 = [
     "tim9",
     "tim10",
     "tim11",
-    "spi3",
-    "spi4",
-    "spi5",
     "usart1",
     "usart2",
     "usart6",
@@ -329,7 +326,6 @@ gpio-f413 = [
     "gpiof",
     "gpiog",
     "gpioh",
-    "aes",
     "can1",
     "can2",
     "can3",
@@ -703,6 +699,7 @@ gpio-f72x = [
     "adc2",
     "adc3",
     "can1",
+    "dac",
     "fmc",
     "gpioc",
     "gpiod",
@@ -759,9 +756,11 @@ gpio-f72x = [
 gpio-f746 = [
     "adc2",
     "adc3",
+    "dac",
     "dma2d",
     "can1",
     "can2",
+    "cec",
     "cryp",
     "dcmi",
     "eth",
@@ -827,9 +826,11 @@ gpio-f746 = [
 gpio-f76x = [
     "adc2",
     "adc3",
+    "dac",
     "dma2d",
     "can1",
     "can2",
+    "cec",
     "cryp",
     "dcmi",
     "eth",
@@ -960,6 +961,7 @@ aes = []
 can1 = []
 can2 = []
 can3 = []
+cec = []
 cryp = []
 cm4 = []
 crs1 = []

src/rcc/enable.rs

@@ -38,6 +38,26 @@ bus! { ETHERNET_MAC => (AHB1, 25, ethmacen, ethmaclpen, ethmacrst),}
 #[cfg(feature = "otg-hs")]
 bus! { OTG_HS_GLOBAL => (AHB1, 29, otghsen, otghslpen, otghsrst),}
 
+#[cfg(feature = "dcmi")]
+bus! { DCMI => (AHB2, 0, dcmien, dcmilpen, dcmirst),}
+
+#[cfg(feature = "jpeg")]
+bus! { JPEG => (AHB2, 1, jpegen, jpeglpen,),}
+
+#[cfg(feature = "f4")]
+#[cfg(feature = "aes")]
+bus! { AES => (AHB2, 4, crypen, , cryprst),}
+
+#[cfg(not(feature = "f4"))]
+#[cfg(feature = "aes")]
+bus! { AES => (AHB2, 4, aesen, aeslpen, aesrst),}
+
+#[cfg(feature = "cryp")]
+bus! { CRYP => (AHB2, 4, crypen, cryplpen, cryprst),}
+
+#[cfg(feature = "hash")]
+bus! { HASH => (AHB2, 5, hashen, hashlpen,),}
+
 #[cfg(feature = "rng")]
 bus! { RNG => (AHB2, 6, rngen, rnglpen, rngrst),}
 
@@ -56,9 +76,7 @@ bus! { FSMC => (AHB3, 0, fmcen, fmclpen, fmcrst),}
 bus! { FSMC => (AHB3, 0, fsmcen, fsmclpen, fsmcrst),}
 
 #[cfg(feature = "quadspi")]
-bus! {
-    QUADSPI => (AHB3, 1, qspien, , qspirst),
-}
+bus! { QUADSPI => (AHB3, 1, qspien, , qspirst),}
 
 #[cfg(feature = "tim2")]
 bus! { TIM2 => (APB1, 0, tim2en, tim2lpen, tim2rst),}
@@ -93,6 +111,9 @@ bus! { SPI2 => (APB1, 14, spi2en, spi2lpen, spi2rst),}
 #[cfg(feature = "spi3")]
 bus! { SPI3 => (APB1, 15, spi3en, spi3lpen, spi3rst),}
 
+#[cfg(feature = "spdifrx")]
+bus! { SPDIFRX => (APB1, 16, spdifrxen, spdifrxlpen, spdifrxrst),}
+
 #[cfg(feature = "usart2")]
 bus! { USART2 => (APB1, 17, usart2en, usart2lpen, usart2rst),}
 #[cfg(feature = "usart3")]
@@ -102,3 +123,150 @@ bus! { USART3 => (APB1, 18, usart3en, usart3lpen, usart3rst),}
 bus! { UART4 => (APB1, 19, uart4en, uart4lpen, uart4rst),}
 #[cfg(feature = "uart5")]
 bus! { UART5 => (APB1, 20, uart5en, uart5lpen, uart5rst),}
+
+bus! { I2C1 => (APB1, 21, i2c1en, i2c1lpen, i2c1rst),}
+#[cfg(feature = "i2c2")]
+bus! { I2C2 => (APB1, 22, i2c2en, i2c2lpen, i2c2rst),}
+#[cfg(feature = "i2c3")]
+bus! { I2C3 => (APB1, 23, i2c3en, i2c3lpen, i2c3rst),}
+#[cfg(feature = "i2c4")]
+bus! { I2C4 => (APB1, 24, i2c4en, i2c4lpen, i2c4rst),}
+#[cfg(feature = "fmpi2c1")]
+#[cfg(not(feature = "svd-f412"))]
+bus! { FMPI2C1 => (APB1, 24, fmpi2c1en, fmpi2c1lpen, fmpi2c1rst),}
+#[cfg(feature = "fmpi2c1")]
+#[cfg(feature = "svd-f412")]
+bus! { FMPI2C1 => (APB1, 24, i2c4en, i2c4lpen, i2c4rst),}
+
+#[cfg(feature = "can1")]
+bus! { CAN1 => (APB1, 25, can1en, can1lpen, can1rst),}
+#[cfg(feature = "can2")]
+bus! { CAN2 => (APB1, 26, can2en, can2lpen, can2rst),}
+
+#[cfg(feature = "f4")]
+#[cfg(feature = "can3")]
+bus! { CAN3 => (APB1, 27, can3en, can3lpen, can3rst),}
+
+#[cfg(feature = "f7")]
+#[cfg(feature = "can3")]
+bus! { CAN3 => (APB1, 13, can3en, can3lpen, can3rst),}
+
+#[cfg(feature = "f4")]
+#[cfg(feature = "cec")]
+bus! { HDMP_CEC => (APB1, 27, cecen, ceclpen, cecrst),}
+
+#[cfg(feature = "f7")]
+#[cfg(feature = "cec")]
+bus! { CEC => (APB1, 27, cecen, ceclpen, cecrst),}
+
+bus! { PWR => (APB1, 28, pwren, pwrlpen, pwrrst),}
+
+#[cfg(feature = "dac")]
+bus! { DAC => (APB1, 29, dacen, daclpen, dacrst),}
+
+#[cfg(feature = "uart7")]
+bus! {UART7 => (APB1, 30, uart7en, uart7lpen, uart7rst),}
+#[cfg(feature = "uart8")]
+bus! {UART8 => (APB1, 31, uart8en, uart8lpen, uart8rst),}
+
+#[cfg(feature = "tim1")]
+bus! { TIM1 => (APB2, 0, tim1en, tim1lpen, tim1rst),}
+#[cfg(feature = "tim8")]
+bus! {TIM8 => (APB2, 1, tim8en, tim8lpen, tim8rst),}
+
+#[cfg(feature = "usart1")]
+bus! { USART1 => (APB2, 4, usart1en, usart1lpen, usart1rst),}
+#[cfg(feature = "usart6")]
+bus! { USART6 => (APB2, 5, usart6en, usart6lpen, usart6rst),}
+#[cfg(feature = "uart9")]
+bus! { UART9 => (APB2, 6, uart9en, uart9lpen, uart9rst),}
+#[cfg(feature = "uart10")]
+bus! { UART10 => (APB2, 7, uart10en, uart10lpen, uart10rst),}
+
+#[cfg(feature = "sdmmc2")]
+bus! { SDMMC2 => (APB2, 7, sdmmc2en, sdmmc2lpen, sdmmc2rst),}
+
+bus! { ADC1 => (APB2, 8, adc1en, adc1lpen, adcrst),}
+
+#[cfg(feature = "adc2")]
+bus! { ADC2 => (APB2, 9, adc2en, adc2lpen, ),}
+#[cfg(feature = "adc2")]
+bus_reset!(ADC2 => 8, adcrst);
+
+#[cfg(feature = "adc3")]
+bus! { ADC3 => (APB2, 10, adc3en, adc3lpen, ),}
+#[cfg(feature = "adc3")]
+bus_reset!(ADC3 => 8, adcrst);
+
+#[cfg(feature = "sdio")]
+bus! { SDIO => (APB2, 11, sdioen, sdiolpen, sdiorst),}
+#[cfg(feature = "sdmmc1")]
+bus! { SDMMC1 => (APB2, 11, sdmmc1en, sdmmc1lpen, sdmmc1rst),}
+
+#[cfg(feature = "spi1")]
+bus! { SPI1 => (APB2, 12, spi1en, spi1lpen, spi1rst),}
+#[cfg(feature = "spi4")]
+bus! { SPI4 => (APB2, 13, spi4en, spi4lpen, spi4rst),}
+
+#[cfg(feature = "sys")]
+bus! { SYSCFG => (APB2, 14, syscfgen, syscfglpen, syscfgrst),}
+
+#[cfg(feature = "tim9")]
+bus! {TIM9 => (APB2, 16, tim9en, tim9lpen, tim9rst),}
+#[cfg(feature = "tim10")]
+bus! { TIM10 => (APB2, 17, tim10en, tim10lpen, tim10rst),}
+#[cfg(feature = "tim11")]
+bus! { TIM11 => (APB2, 18, tim11en, tim11lpen, tim11rst),}
+
+#[cfg(feature = "spi5")]
+bus! { SPI5 => (APB2, 20, spi5en, spi5lpen, spi5rst),}
+#[cfg(feature = "spi6")]
+bus! { SPI6 => (APB2, 21, spi6en, spi6lpen, spi6rst),}
+
+#[cfg(any(
+    feature = "gpio-f413",
+    feature = "gpio-f469",
+    feature = "stm32f429",
+    feature = "stm32f439"
+))]
+#[cfg(feature = "sai1")]
+bus! {
+    SAI => (APB2, 22, sai1en, sai1lpen, sai1rst),
+}
+
+#[cfg(not(any(
+    feature = "gpio-f413",
+    feature = "gpio-f469",
+    feature = "stm32f429",
+    feature = "stm32f439"
+)))]
+#[cfg(feature = "sai1")]
+bus! {
+    SAI1 => (APB2, 22, sai1en, sai1lpen, sai1rst),
+}
+
+#[cfg(feature = "sai2")]
+bus! {
+SAI2 => (APB2, 23, sai2en, sai2lpen, sai2rst),}
+
+#[cfg(feature = "f4")]
+#[cfg(feature = "dfsdm1")]
+bus! { DFSDM => (APB2, 24, dfsdmen, dfsdmlpen, dfsdmrst),}
+#[cfg(feature = "f4")]
+#[cfg(feature = "dfsdm2")]
+bus! { DFSDM => (APB2, 25, dfsdmen, dfsdmlpen, dfsdmrst),}
+
+#[cfg(feature = "ltdc")]
+bus! { LTDC => (APB2, 26, ltdcen, ltdclpen, ltdcrst),}
+
+#[cfg(feature = "dsihost")]
+bus! { DSI => (APB2, 27, dsien, dsilpen, dsirst),}
+
+#[cfg(feature = "f7")]
+#[cfg(feature = "dfsdm1")]
+bus! { DFSDM => (APB2, 29, dfsdm1en, dfsdm1lpen, dfsdm1rst),}
+
+#[cfg(feature = "mdios")]
+bus! { MDIOS => (APB2, 30, mdioen, mdiolpen, mdiorst),}
+#[cfg(feature = "svd-f730")]
+bus! { USBPHYC => (APB2, 31, usbphycen,, usbphycrst),}

src/rcc/f4/enable.rs

@@ -9,8 +9,6 @@ use fugit::RateExtU32;
 
 mod pll;
 
-mod enable;
-
 bus_struct! {
     APB1 => (APB1ENR, apb1enr, APB1LPENR, apb1lpenr, APB1RSTR, apb1rstr, "Advanced Peripheral Bus 1 (APB1) registers"),
     APB2 => (APB2ENR, apb2enr, APB2LPENR, apb2lpenr, APB2RSTR, apb2rstr, "Advanced Peripheral Bus 2 (APB2) registers"),