restore DMA generics order

Author: burrbull

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- `DmaSet` & `Transfer` take channel after stream generic, then other [#477]
 - Depracate "rt" feature as enabled by-default in `pac` [#476]
 - Add `Pin::interrupt()` helper method [#476]
 - Add restriction for setting pins in alternate mode (`IntoAF`), add docs [#474]
@@ -45,6 +46,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#473]: https://github.com/stm32-rs/stm32f4xx-hal/pull/473
 [#474]: https://github.com/stm32-rs/stm32f4xx-hal/pull/474
 [#476]: https://github.com/stm32-rs/stm32f4xx-hal/pull/476
+[#477]: https://github.com/stm32-rs/stm32f4xx-hal/pull/477
 
 ## [v0.12.0] - 2022-02-23
 

examples/adc_dma_rtic.rs

@@ -25,7 +25,7 @@ mod app {
     type MyMono = DwtSystick<MONO_HZ>;
 
     type DMATransfer =
-        Transfer<Stream0<DMA2>, Adc<ADC1>, PeripheralToMemory, &'static mut [u16; 2], 0>;
+        Transfer<Stream0<DMA2>, 0, Adc<ADC1>, PeripheralToMemory, &'static mut [u16; 2]>;
 
     #[shared]
     struct Shared {

examples/i2s-audio-out-dma.rs

@@ -51,12 +51,12 @@ use stm32_i2s_v12x::{MasterClock, MasterConfig, Polarity, TransmitMode};
 use stm32f4xx_hal::dma::config::DmaConfig;
 use stm32f4xx_hal::dma::MemoryToPeripheral;
 use stm32f4xx_hal::dma::{Stream5, StreamsTuple, Transfer};
-use stm32f4xx_hal::gpio::{Alternate, PA4, PC10, PC12, PC7};
+use stm32f4xx_hal::gpio::{AF6, PA4, PC10, PC12, PC7};
 use stm32f4xx_hal::i2c::I2c;
-use stm32f4xx_hal::i2s::I2s;
+use stm32f4xx_hal::i2s::I2s3;
+use stm32f4xx_hal::pac::DMA1;
 use stm32f4xx_hal::pac::{interrupt, Interrupt};
 use stm32f4xx_hal::pac::{CorePeripherals, Peripherals};
-use stm32f4xx_hal::pac::{DMA1, SPI3};
 use stm32f4xx_hal::prelude::*;
 
 use cs43l22::{Cs43L22, Register};
@@ -210,21 +210,13 @@ fn main() -> ! {
 
 type I2sDmaTransfer = Transfer<
     Stream5<DMA1>,
+    0,
     stm32_i2s_v12x::I2s<
-        I2s<
-            SPI3,
-            (
-                PA4<Alternate<6>>,
-                PC10<Alternate<6>>,
-                PC7<Alternate<6>>,
-                PC12<Alternate<6>>,
-            ),
-        >,
+        I2s3<(PA4<AF6>, PC10<AF6>, PC7<AF6>, PC12<AF6>)>,
         TransmitMode<Data16Frame16>,
     >,
     MemoryToPeripheral,
     &'static mut [u16; SINE_SAMPLES * 2],
-    0,
 >;
 
 /// DMA transfer handoff from main() to interrupt handler

examples/spi_dma.rs

@@ -20,10 +20,10 @@ const ARRAY_SIZE: usize = 100;
 
 type SpiDma = Transfer<
     Stream4<pac::DMA1>,
+    0,
     Tx<pac::SPI2>,
     MemoryToPeripheral,
     &'static mut [u8; ARRAY_SIZE],
-    0,
 >;
 
 static G_TRANSFER: Mutex<RefCell<Option<SpiDma>>> = Mutex::new(RefCell::new(None));

src/dma/mod.rs

@@ -869,7 +869,7 @@ pub mod config {
 }
 
 /// DMA Transfer.
-pub struct Transfer<STREAM, PERIPHERAL, DIRECTION, BUF, const CHANNEL: u8>
+pub struct Transfer<STREAM, const CHANNEL: u8, PERIPHERAL, DIRECTION, BUF>
 where
     STREAM: Stream,
     PERIPHERAL: PeriAddress,
@@ -883,12 +883,12 @@ where
     transfer_length: u16,
 }
 
-impl<STREAM, PERIPHERAL, BUF, const CHANNEL: u8>
-    Transfer<STREAM, PERIPHERAL, MemoryToPeripheral, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, BUF>
+    Transfer<STREAM, CHANNEL, PERIPHERAL, MemoryToPeripheral, BUF>
 where
     STREAM: Stream,
     ChannelX<CHANNEL>: Channel,
-    PERIPHERAL: PeriAddress + DMASet<STREAM, MemoryToPeripheral, CHANNEL>,
+    PERIPHERAL: PeriAddress + DMASet<STREAM, CHANNEL, MemoryToPeripheral>,
     BUF: ReadBuffer<Word = <PERIPHERAL as PeriAddress>::MemSize>,
 {
     /// Configures the DMA stream to the correct channel for the peripheral, configures source and
@@ -1014,12 +1014,12 @@ where
     }
 }
 
-impl<STREAM, PERIPHERAL, BUF, const CHANNEL: u8>
-    Transfer<STREAM, PERIPHERAL, PeripheralToMemory, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, BUF>
+    Transfer<STREAM, CHANNEL, PERIPHERAL, PeripheralToMemory, BUF>
 where
     STREAM: Stream,
     ChannelX<CHANNEL>: Channel,
-    PERIPHERAL: PeriAddress + DMASet<STREAM, PeripheralToMemory, CHANNEL> + SafePeripheralRead,
+    PERIPHERAL: PeriAddress + DMASet<STREAM, CHANNEL, PeripheralToMemory> + SafePeripheralRead,
     BUF: WriteBuffer<Word = <PERIPHERAL as PeriAddress>::MemSize>,
 {
     /// Access the owned peripheral for reading
@@ -1028,12 +1028,12 @@ where
     }
 }
 
-impl<STREAM, PERIPHERAL, BUF, const CHANNEL: u8>
-    Transfer<STREAM, PERIPHERAL, PeripheralToMemory, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, BUF>
+    Transfer<STREAM, CHANNEL, PERIPHERAL, PeripheralToMemory, BUF>
 where
     STREAM: Stream,
     ChannelX<CHANNEL>: Channel,
-    PERIPHERAL: PeriAddress + DMASet<STREAM, PeripheralToMemory, CHANNEL>,
+    PERIPHERAL: PeriAddress + DMASet<STREAM, CHANNEL, PeripheralToMemory>,
     BUF: WriteBuffer<Word = <PERIPHERAL as PeriAddress>::MemSize>,
 {
     /// Configures the DMA stream to the correct channel for the peripheral, configures source and
@@ -1162,12 +1162,12 @@ where
     }
 }
 
-impl<STREAM, PERIPHERAL, BUF, S, const CHANNEL: u8>
-    Transfer<STREAM, PERIPHERAL, MemoryToMemory<S>, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, BUF, S>
+    Transfer<STREAM, CHANNEL, PERIPHERAL, MemoryToMemory<S>, BUF>
 where
     STREAM: Stream,
     ChannelX<CHANNEL>: Channel,
-    PERIPHERAL: PeriAddress + DMASet<STREAM, MemoryToMemory<S>, CHANNEL>,
+    PERIPHERAL: PeriAddress + DMASet<STREAM, CHANNEL, MemoryToMemory<S>>,
     MemoryToMemory<S>: PeriAddress,
     BUF: WriteBuffer<Word = <PERIPHERAL as PeriAddress>::MemSize>,
 {
@@ -1261,13 +1261,13 @@ where
     }
 }
 
-impl<STREAM, PERIPHERAL, DIR, BUF, const CHANNEL: u8>
-    Transfer<STREAM, PERIPHERAL, DIR, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, DIR, BUF>
+    Transfer<STREAM, CHANNEL, PERIPHERAL, DIR, BUF>
 where
     STREAM: Stream,
     ChannelX<CHANNEL>: Channel,
     DIR: Direction,
-    PERIPHERAL: PeriAddress + DMASet<STREAM, DIR, CHANNEL>,
+    PERIPHERAL: PeriAddress + DMASet<STREAM, CHANNEL, DIR>,
 {
     /// Starts the transfer, the closure will be executed right after enabling the stream.
     pub fn start<F>(&mut self, f: F)
@@ -1589,8 +1589,8 @@ where
     }
 }
 
-impl<STREAM, PERIPHERAL, DIR, BUF, const CHANNEL: u8> Drop
-    for Transfer<STREAM, PERIPHERAL, DIR, BUF, CHANNEL>
+impl<STREAM, const CHANNEL: u8, PERIPHERAL, DIR, BUF> Drop
+    for Transfer<STREAM, CHANNEL, PERIPHERAL, DIR, BUF>
 where
     STREAM: Stream,
     PERIPHERAL: PeriAddress,

src/dma/traits.rs

@@ -291,14 +291,14 @@ pub trait Channel {}
 /// # Safety
 ///
 /// Memory corruption might occur if this trait is implemented for an invalid combination.
-pub unsafe trait DMASet<STREAM, DIRECTION, const CHANNEL: u8> {}
+pub unsafe trait DMASet<STREAM, const CHANNEL: u8, DIRECTION> {}
 
 tim_channels!(CCR1, CCR2, CCR3, CCR4, DMAR, ARR);
 
 macro_rules! dma_map {
     ($(($Stream:ty, $C:literal, $Peripheral:ty, $Dir:ty)),+ $(,)*) => {
         $(
-            unsafe impl DMASet<$Stream, $Dir, $C> for $Peripheral {}
+            unsafe impl DMASet<$Stream, $C, $Dir> for $Peripheral {}
         )+
     };
 }

src/i2s.rs

@@ -275,10 +275,10 @@ mod dma {
     }
 
     /// DMA is available for I2S based on the underlying implementations for SPI
-    unsafe impl<SPI, PINS, MODE, STREAM, DIR, const CHANNEL: u8> DMASet<STREAM, DIR, CHANNEL>
+    unsafe impl<SPI, PINS, MODE, STREAM, const CHANNEL: u8, DIR> DMASet<STREAM, CHANNEL, DIR>
         for stm32_i2s_v12x::I2s<I2s<SPI, PINS>, MODE>
     where
-        SPI: DMASet<STREAM, DIR, CHANNEL>,
+        SPI: DMASet<STREAM, CHANNEL, DIR>,
     {
     }
 }