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use bitflags for DmaFlags, DmaCommonInterrupts and other flags and events
1 parent 2d8d882 commit cb5903f

22 files changed

+849
-668
lines changed

CHANGELOG.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1010
### Changed
1111

1212
- complete and rework Dma Stream API [#666]
13+
- Use `enumflags2::BitFlags` for interrupt flags and events [#673]
1314
- SPI bidi takes 2 pins [#526]
1415
- `Fast Read Quad I/O (EBh)` in `qspi-w25q` example now matches W25QXX datasheet. [#682]
1516
- `embedded-storage` version bumped to 0.3
@@ -25,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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2627
[#526]: https://github.com/stm32-rs/stm32f4xx-hal/pull/526
2728
[#666]: https://github.com/stm32-rs/stm32f4xx-hal/pull/666
29+
[#673]: https://github.com/stm32-rs/stm32f4xx-hal/pull/673
2830
[#677]: https://github.com/stm32-rs/stm32f4xx-hal/pull/677
2931
[#678]: https://github.com/stm32-rs/stm32f4xx-hal/pull/678
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[#682]: https://github.com/stm32-rs/stm32f4xx-hal/pull/682

Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ fugit = "0.3.6"
4646
fugit-timer = "0.1.3"
4747
rtic-monotonic = { version = "1.0", optional = true }
4848
systick-monotonic = { version = "1.0", optional = true }
49-
bitflags = "2.2"
49+
enumflags2 = "0.7.8"
5050
embedded-storage = "0.3"
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vcell = "0.1.3"
5252

examples/analog-stopwatch-with-spi-ssd1306.rs

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ use crate::hal::{
1515
interrupt, pac,
1616
prelude::*,
1717
rcc::{Clocks, Rcc},
18-
spi::Spi,
19-
timer::{CounterUs, Event, FTimer, Timer},
18+
spi::{Mode, Phase, Polarity, Spi},
19+
timer::{CounterUs, Event, FTimer, Flag, Timer},
2020
};
2121

2222
use core::cell::{Cell, RefCell};
@@ -25,8 +25,6 @@ use core::ops::DerefMut;
2525
use cortex_m::interrupt::{free, CriticalSection, Mutex};
2626
use heapless::String;
2727

28-
use hal::spi::{Mode, Phase, Polarity};
29-
3028
use core::f32::consts::{FRAC_PI_2, PI};
3129
use cortex_m_rt::{entry, exception, ExceptionFrame};
3230
use embedded_graphics::{
@@ -263,7 +261,7 @@ fn EXTI0() {
263261
fn TIM2() {
264262
free(|cs| {
265263
if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
266-
tim2.clear_interrupt(Event::Update);
264+
tim2.clear_flags(Flag::Update);
267265
}
268266

269267
let cell = ELAPSED_MS.borrow(cs);

examples/rtic-serial-dma-rx-idle.rs

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
mod app {
1515

1616
use hal::{
17-
dma::{config::DmaConfig, PeripheralToMemory, Stream2, StreamsTuple, Transfer},
17+
dma::{config::DmaConfig, DmaFlag, PeripheralToMemory, Stream2, StreamsTuple, Transfer},
1818
pac::{DMA2, USART1},
1919
prelude::*,
2020
rcc::RccExt,
@@ -140,12 +140,9 @@ mod app {
140140
fn dma2_stream2(mut cx: dma2_stream2::Context) {
141141
let transfer = &mut cx.shared.rx_transfer;
142142

143-
if transfer.is_fifo_error() {
144-
transfer.clear_fifo_error();
145-
}
146-
if transfer.is_transfer_complete() {
147-
transfer.clear_transfer_complete();
148-
143+
let flags = transfer.flags();
144+
transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
145+
if flags.is_transfer_complete() {
149146
// Buffer is full, but no IDLE received!
150147
// You can process this data or discard data (ignore transfer complete interrupt and wait IDLE).
151148

examples/rtic-spi-slave-dma.rs

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ mod app {
99
use embedded_hal::spi::{Mode, Phase, Polarity};
1010
use hal::{
1111
dma::{
12-
config::DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream0, Stream5,
12+
config::DmaConfig, DmaFlag, MemoryToPeripheral, PeripheralToMemory, Stream0, Stream5,
1313
StreamsTuple, Transfer,
1414
},
1515
gpio::{gpioc::PC13, GpioExt, Output, PushPull},
@@ -142,12 +142,9 @@ mod app {
142142
let mut led = cx.shared.led;
143143
let rx_buffer = cx.local.rx_buffer;
144144
rx_transfer.lock(|transfer| {
145-
if transfer.is_fifo_error() {
146-
transfer.clear_fifo_error();
147-
}
148-
if transfer.is_transfer_complete() {
149-
transfer.clear_transfer_complete();
150-
145+
let flags = transfer.flags();
146+
transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
147+
if flags.is_transfer_complete() {
151148
let (filled_buffer, _) = transfer.next_transfer(rx_buffer.take().unwrap()).unwrap();
152149
match filled_buffer[0] {
153150
1 => led.lock(|led| led.set_low()),
@@ -164,11 +161,9 @@ mod app {
164161
let mut tx_transfer = cx.shared.tx_transfer;
165162
let tx_buffer = cx.local.tx_buffer;
166163
tx_transfer.lock(|transfer| {
167-
if transfer.is_fifo_error() {
168-
transfer.clear_fifo_error();
169-
}
170-
if transfer.is_transfer_complete() {
171-
transfer.clear_transfer_complete();
164+
let flags = transfer.flags();
165+
transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
166+
if flags.is_transfer_complete() {
172167
let (filled_buffer, _) = transfer.next_transfer(tx_buffer.take().unwrap()).unwrap();
173168
*tx_buffer = Some(filled_buffer);
174169
}

examples/rtic-usart-shell-ssd1306.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ mod usart_shell {
2626
pac::I2C1,
2727
pac::USART1,
2828
prelude::*,
29-
serial::{config::Config, Event::Rxne, Serial},
29+
serial::{self, config::Config, Serial},
3030
timer::Event,
3131
};
3232

@@ -110,7 +110,7 @@ mod usart_shell {
110110
)
111111
.unwrap()
112112
.with_u8_data();
113-
serial.listen(Rxne);
113+
serial.listen(serial::Event::RxNotEmpty);
114114
// ushell
115115
let autocomplete = StaticAutocomplete(["clear", "help", "off", "on", "status"]);
116116
let history = LRUHistory::default();

examples/rtic-usart-shell.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ mod usart_shell {
1313
gpio::{gpioa::PA0, gpioc::PC13, Edge, Input, Output, PushPull},
1414
pac::USART1,
1515
prelude::*,
16-
serial::{config::Config, Event::Rxne, Serial},
16+
serial::{self, config::Config, Serial},
1717
};
1818

1919
use ushell::{
@@ -76,7 +76,7 @@ mod usart_shell {
7676
)
7777
.unwrap()
7878
.with_u8_data();
79-
serial.listen(Rxne);
79+
serial.listen(serial::Event::RxNotEmpty);
8080
// ushell
8181
let autocomplete = StaticAutocomplete(["clear", "help", "off", "on", "status"]);
8282
let history = LRUHistory::default();

examples/spi-dma.rs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
// Halt on panic
55
use panic_halt as _;
6+
use stm32f4xx_hal::dma::DmaFlag;
67

78
use core::cell::RefCell;
89
use cortex_m::interrupt::Mutex;
@@ -100,12 +101,10 @@ fn DMA2_STREAM4() {
100101
cortex_m::interrupt::free(|cs| G_TRANSFER.borrow(cs).replace(None).unwrap())
101102
});
102103

104+
let flags = transfer.flags();
103105
// Its important to clear fifo errors as the transfer is paused until it is cleared
104-
if transfer.is_fifo_error() {
105-
transfer.clear_fifo_error();
106-
}
107-
if transfer.is_transfer_complete() {
108-
transfer.clear_transfer_complete();
106+
transfer.clear_flags(DmaFlag::FifoError | DmaFlag::TransferComplete);
107+
if flags.is_transfer_complete() {
109108
unsafe {
110109
static mut BUFFER: [u8; ARRAY_SIZE] = [0; ARRAY_SIZE];
111110
for (i, b) in BUFFER.iter_mut().enumerate() {

examples/stopwatch-with-ssd1306-and-interrupts-and-dma-i2c.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ use crate::hal::{
3030
pac::{DMA1, I2C1},
3131
prelude::*,
3232
rcc::{Clocks, Rcc},
33-
timer::{CounterUs, Event, Timer},
33+
timer::{CounterUs, Event, Flag, Timer},
3434
};
3535
use core::cell::{Cell, RefCell};
3636
use core::fmt::Write;
@@ -265,7 +265,7 @@ fn main() -> ! {
265265
fn TIM2() {
266266
free(|cs| {
267267
if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
268-
tim2.clear_interrupt(Event::Update);
268+
tim2.clear_flags(Flag::Update);
269269
}
270270

271271
let cell = ELAPSED_MS.borrow(cs);

examples/stopwatch-with-ssd1306-and-interrupts.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ use crate::hal::{
2727
interrupt, pac,
2828
prelude::*,
2929
rcc::{Clocks, Rcc},
30-
timer::{CounterUs, Event, Timer},
30+
timer::{CounterUs, Event, Flag, Timer},
3131
};
3232
use core::cell::{Cell, RefCell};
3333
use core::fmt::Write;
@@ -148,7 +148,7 @@ fn main() -> ! {
148148
fn TIM2() {
149149
free(|cs| {
150150
if let Some(ref mut tim2) = TIMER_TIM2.borrow(cs).borrow_mut().deref_mut() {
151-
tim2.clear_interrupt(Event::Update);
151+
tim2.clear_flags(Flag::Update);
152152
}
153153

154154
let cell = ELAPSED_MS.borrow(cs);

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