extend Delay

Author: burrbull

CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Extend timers to 32bit on `Delay`
 - Move `MonoTimer` from `timer` to dwt mode [#448]
 - Unify serial trait impls for embedded-hal 0.2 & 1.0 [#447]
 - Add possibility to select Timer master mode

src/timer.rs

@@ -101,15 +101,15 @@ pub trait TimerExt: Sized {
     fn delay<const FREQ: u32>(self, clocks: &Clocks) -> FDelay<Self, FREQ>;
     /// Blocking [Delay] with fixed precision of 1 ms (1 kHz sampling)
     ///
-    /// Can wait from 2 ms to 65 sec for 16-bit timer and from 2 ms to 49 days for 32-bit timer.
+    /// Can wait from 2 ms to 49 days.
     ///
     /// NOTE: don't use this if your system frequency more than 65 MHz
     fn delay_ms(self, clocks: &Clocks) -> DelayMs<Self> {
         self.delay::<1_000>(clocks)
     }
     /// Blocking [Delay] with fixed precision of 1 μs (1 MHz sampling)
     ///
-    /// Can wait from 2 μs to 65 ms for 16-bit timer and from 2 μs to 71 min for 32-bit timer.
+    /// Can wait from 2 μs to 71 min.
     fn delay_us(self, clocks: &Clocks) -> DelayUs<Self> {
         self.delay::<1_000_000>(clocks)
     }

src/timer/delay.rs

@@ -115,19 +115,25 @@ pub type DelayMs<TIM> = FDelay<TIM, 1_000>;
 impl<TIM: Instance, const FREQ: u32> FDelay<TIM, FREQ> {
     /// Sleep for given time
     pub fn delay(&mut self, time: TimerDurationU32<FREQ>) -> Result<(), Error> {
-        // Write Auto-Reload Register (ARR)
-        self.tim.set_auto_reload(time.ticks() - 1)?;
+        let mut ticks = time.ticks() - 1;
+        while ticks > 0 {
+            let reload = ticks.min(TIM::max_auto_reload());
+            ticks -= reload;
 
-        // Trigger update event (UEV) in the event generation register (EGR)
-        // in order to immediately apply the config
-        self.tim.trigger_update();
+            // Write Auto-Reload Register (ARR)
+            self.tim.set_auto_reload(reload)?;
 
-        // Configure the counter in one-pulse mode (counter stops counting at
-        // the next updateevent, clearing the CEN bit) and enable the counter.
-        self.tim.start_one_pulse();
+            // Trigger update event (UEV) in the event generation register (EGR)
+            // in order to immediately apply the config
+            self.tim.trigger_update();
 
-        // Wait for CEN bit to clear
-        while self.tim.is_counter_enabled() { /* wait */ }
+            // Configure the counter in one-pulse mode (counter stops counting at
+            // the next updateevent, clearing the CEN bit) and enable the counter.
+            self.tim.start_one_pulse();
+
+            // Wait for CEN bit to clear
+            while self.tim.is_counter_enabled() { /* wait */ }
+        }
 
         Ok(())
     }