Merge #430

430: fugit-rate & PERExt traits r=therealprof a=burrbull

Require korken89/fugit#18

Co-authored-by: Andrey Zgarbul <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Move `i2c` `embedded-hal` trait impls to `I2c` methods [#431]
 - Reexport pins in `gpio` module
 - Pwm channels now constants [#432]
+- Use fugit rate types instead of custom [#430]
 - Add channel events, make Event use bitflags (simplify interrupt handling) [#425]
 - reexport `digital::v2::PinState` again [#428]
 - Timer impls with time based on `fugit` moved to `fugit` module, added `Pwm` and `fugit-timer` impls [#423]
@@ -55,6 +56,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#440]: https://github.com/stm32-rs/stm32f4xx-hal/pull/440
 [#443]: https://github.com/stm32-rs/stm32f4xx-hal/pull/443
 [#441]: https://github.com/stm32-rs/stm32f4xx-hal/pull/441
+[#430]: https://github.com/stm32-rs/stm32f4xx-hal/pull/430
 
 ### Changed
 

Cargo.toml

@@ -41,7 +41,7 @@ cast = { default-features = false, version = "0.3.0" }
 void = { default-features = false, version = "1.0.2" }
 embedded-hal = { features = ["unproven"], version = "0.2.7" }
 display-interface = { version = "0.4.1", optional = true }
-fugit = "0.3.3"
+fugit = "0.3.5"
 fugit-timer = "0.1.3"
 rtic-monotonic = { version = "1.0", optional = true }
 bitflags = "1.3.2"

examples/adc_dma_rtic.rs

@@ -44,12 +44,12 @@ mod app {
         let rcc = device.RCC.constrain();
         let _clocks = rcc
             .cfgr
-            .use_hse(25.mhz())
+            .use_hse(25.MHz())
             .require_pll48clk()
-            .sysclk(84.mhz())
-            .hclk(84.mhz())
-            .pclk1(42.mhz())
-            .pclk2(84.mhz())
+            .sysclk(MONO_HZ.Hz())
+            .hclk(MONO_HZ.Hz())
+            .pclk1(42.MHz())
+            .pclk2(84.MHz())
             .freeze();
 
         let mut dcb = cx.core.DCB;

examples/analog-stopwatch-with-spi-ssd1306.rs

@@ -101,7 +101,7 @@ fn main() -> ! {
             polarity: Polarity::IdleLow,
             phase: Phase::CaptureOnFirstTransition,
         },
-        2000.khz(),
+        2000.kHz(),
         &clocks,
     );
 
@@ -209,10 +209,10 @@ fn main() -> ! {
 
 fn setup_clocks(rcc: Rcc) -> Clocks {
     rcc.cfgr
-        .hclk(180.mhz())
-        .sysclk(180.mhz())
-        .pclk1(45.mhz())
-        .pclk2(90.mhz())
+        .hclk(180.MHz())
+        .sysclk(180.MHz())
+        .pclk1(45.MHz())
+        .pclk2(90.MHz())
         .freeze()
 }
 

examples/blinky-timer-irq.rs

@@ -67,7 +67,7 @@ fn main() -> ! {
     let dp = Peripherals::take().unwrap();
 
     let rcc = dp.RCC.constrain();
-    let clocks = rcc.cfgr.sysclk(16.mhz()).pclk1(8.mhz()).freeze();
+    let clocks = rcc.cfgr.sysclk(16.MHz()).pclk1(8.MHz()).freeze();
 
     // Configure PA5 pin to blink LED
     let gpioa = dp.GPIOA.split();

examples/can-send.rs

@@ -10,7 +10,7 @@ use bxcan::filter::Mask32;
 use bxcan::{Frame, StandardId};
 use cortex_m_rt::entry;
 use nb::block;
-use stm32f4xx_hal::{can::Can, pac, prelude::*};
+use stm32f4xx_hal::{pac, prelude::*};
 
 #[entry]
 fn main() -> ! {
@@ -21,14 +21,16 @@ fn main() -> ! {
     // To meet CAN clock accuracy requirements an external crystal or ceramic
     // resonator must be used. The blue pill has a 8MHz external crystal.
     // Other boards might have a crystal with another frequency or none at all.
-    rcc.cfgr.use_hse(8.mhz()).freeze();
+    rcc.cfgr.use_hse(8.MHz()).freeze();
 
     let gpiob = dp.GPIOB.split();
     let mut can1 = {
         let rx = gpiob.pb8.into_alternate::<9>();
         let tx = gpiob.pb9.into_alternate();
 
-        let can = Can::new(dp.CAN1, (tx, rx));
+        // let can = Can::new(dp.CAN1, (tx, rx));
+        // or
+        let can = dp.CAN1.can((tx, rx));
 
         bxcan::Can::builder(can)
             // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5%
@@ -45,7 +47,7 @@ fn main() -> ! {
         let tx = gpiob.pb13.into_alternate();
         let rx = gpiob.pb12.into_alternate();
 
-        let can = Can::new(dp.CAN2, (tx, rx));
+        let can = dp.CAN2.can((tx, rx));
 
         let can2 = bxcan::Can::builder(can)
             // APB1 (PCLK1): 8MHz, Bit rate: 500kBit/s, Sample Point 87.5%

examples/delay-syst-blinky.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on SysTick
         let mut delay = hal::delay::Delay::new(cp.SYST, &clocks);

examples/delay-timer-blinky.rs

@@ -25,7 +25,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.use_hse(25.mhz()).sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.use_hse(25.MHz()).sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on general-pupose 32-bit timer TIM5
         let mut delay = dp.TIM5.delay_us(&clocks);

examples/dwt-blinky.rs

@@ -26,7 +26,7 @@ fn main() -> ! {
 
         // Set up the system clock. We want to run at 48MHz for this one.
         let rcc = dp.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(48.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(48.MHz()).freeze();
 
         // Create a delay abstraction based on DWT cycle counter
         let dwt = cp.DWT.constrain(cp.DCB, &clocks);

examples/f413disco_lcd_ferris.rs

@@ -706,7 +706,7 @@ fn main() -> ! {
 
         // Configure and lock the clocks at maximum warp
         let rcc = p.RCC.constrain();
-        let clocks = rcc.cfgr.sysclk(100.mhz()).freeze();
+        let clocks = rcc.cfgr.sysclk(100.MHz()).freeze();
 
         // Define the pins we need for our 16bit parallel bus
         let lcd_pins = LcdPins {