diff --git a/CHANGELOG.md b/CHANGELOG.md
index db1c5410..21762b39 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
  - IrDA mode for USARTs [#761]
  - initial `SAI` support [#248]
  - initial `embedded-io` support [#725]
+ - add `.set_cms()` and `CenterAlignedMode` enum for PWM. [#697]
 
 ### Changed
 
@@ -38,6 +39,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 [#248]: https://github.com/stm32-rs/stm32f4xx-hal/pull/248
 [#566]: https://github.com/stm32-rs/stm32f4xx-hal/pull/566
+[#697]: https://github.com/stm32-rs/stm32f4xx-hal/pull/697
 [#706]: https://github.com/stm32-rs/stm32f4xx-hal/pull/706
 [#725]: https://github.com/stm32-rs/stm32f4xx-hal/pull/725
 [#731]: https://github.com/stm32-rs/stm32f4xx-hal/pull/731
diff --git a/src/timer.rs b/src/timer.rs
index 3f7c3045..29f4818b 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -306,6 +306,9 @@ pub enum Ocm {
     PwmMode2 = 7,
 }
 
+// Center-aligned mode selection
+pub use pac::tim1::cr1::CMS as CenterAlignedMode;
+
 /// Wrapper type that indicates which register of the contained timer to use for DMA.
 pub struct CCR<T, const C: u8>(T);
 pub type CCR1<T> = CCR<T, 0>;
@@ -317,7 +320,7 @@ pub type CCR4<T> = CCR<T, 3>;
 pub struct DMAR<T>(T);
 
 mod sealed {
-    use super::{BitFlags, Event, Flag, IdleState, Ocm, Polarity};
+    use super::{BitFlags, CenterAlignedMode, Event, Flag, IdleState, Ocm, Polarity};
     pub trait General {
         type Width: Into<u32> + From<u16>;
         fn max_auto_reload() -> u32;
@@ -361,6 +364,7 @@ mod sealed {
         fn set_dtg_value(value: u8);
         fn read_dtg_value() -> u8;
         fn idle_state(channel: u8, comp: bool, s: IdleState);
+        fn set_cms(mode: CenterAlignedMode);
     }
 
     pub trait WithPwm: WithPwmCommon {
@@ -605,6 +609,11 @@ macro_rules! hal {
                             }
                         }
                     }
+                    #[inline(always)]
+                    fn set_cms(cms: CenterAlignedMode) {
+                        let tim = unsafe { &*<$TIM>::ptr() };
+                        tim.cr1().write(|w| w.cms().variant(cms));
+                    }
                 }
             )?
 
diff --git a/src/timer/pwm.rs b/src/timer/pwm.rs
index a8790cd4..0943d15a 100644
--- a/src/timer/pwm.rs
+++ b/src/timer/pwm.rs
@@ -37,8 +37,8 @@
 
 use super::sealed::Split;
 use super::{
-    compute_arr_presc, Advanced, CPin, FTimer, IdleState, Instance, NCPin, Ocm, Polarity, Timer,
-    WithPwm,
+    compute_arr_presc, Advanced, CPin, CenterAlignedMode, FTimer, IdleState, Instance, NCPin, Ocm,
+    Polarity, Timer, WithPwm,
 };
 pub use super::{Ch, C1, C2, C3, C4};
 use crate::gpio::{OpenDrain, PushPull};
@@ -494,6 +494,14 @@ macro_rules! impl_advanced {
         pub fn get_dead_time_bits(&self) -> u8 {
             TIM::read_dtg_value()
         }
+
+        /// Sets the alignment mode
+        #[inline]
+        pub fn set_cms(&mut self, mode: CenterAlignedMode) {
+            self.tim.enable_counter(false);
+            TIM::set_cms(mode);
+            self.tim.enable_counter(true);
+        }
     };
 }