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1 parent 51f720a commit 08678ccCopy full SHA for 08678cc
src/rcc.rs
@@ -263,6 +263,14 @@ impl CFGR {
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let flash = unsafe { &(*FLASH::ptr()) };
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let rcc = unsafe { &(*RCC::ptr()) };
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+ // Switch to fail-safe clock settings.
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+ // This is useful when booting from a bootloader that alters clock tree configuration.
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+ // Turn on HSI
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+ rcc.cr.modify(|_, w| w.hsion().set_bit());
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+ while rcc.cr.read().hsirdy().bit_is_clear() {}
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+ // Switch to HSI
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+ rcc.cfgr.modify(|_, w| w.sw().hsi());
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+
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// If HSE is provided by the user
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let hse_freq: u32 = self.hse.as_ref().map_or(0, |c| c.freq);
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// SYSCLK, must be <= 216 Mhz. By default, HSI frequency is chosen
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