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Fixed the CAN timing on the examples
1 parent 70d3b2c commit 56e92d6

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2 files changed

+16
-10
lines changed

2 files changed

+16
-10
lines changed

examples/can-echo.rs

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,11 @@ fn main() -> ! {
2525
// To meet CAN clock accuracy requirements an external crystal or ceramic
2626
// resonator must be used. The blue pill has a 8MHz external crystal.
2727
// Other boards might have a crystal with another frequency or none at all.
28-
rcc.cfgr
29-
.hse(HSEClock::new(8.mhz(), HSEClockMode::Bypass))
28+
let _clocks = rcc
29+
.cfgr
30+
.hse(HSEClock::new(25.mhz(), HSEClockMode::Bypass))
31+
.sysclk(216.mhz())
32+
.hclk(216.mhz())
3033
.freeze();
3134

3235
let gpioa = dp.GPIOA.split();
@@ -40,9 +43,9 @@ fn main() -> ! {
4043
bxcan::Can::new(can)
4144
};
4245
can1.configure(|config| {
43-
// APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5%
46+
// APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
4447
// Value was calculated with http://www.bittiming.can-wiki.info/
45-
config.set_bit_timing(0x001c_0003);
48+
config.set_bit_timing(0x001e_000b);
4649
});
4750

4851
// Configure filters so that can frames can be received.
@@ -57,9 +60,9 @@ fn main() -> ! {
5760

5861
let mut can2 = bxcan::Can::new(can);
5962
can2.configure(|config| {
60-
// APB1 (PCLK1): 8MHz, Bit rate: 125kBit/s, Sample Point 87.5%
63+
// APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
6164
// Value was calculated with http://www.bittiming.can-wiki.info/
62-
config.set_bit_timing(0x001c_0003);
65+
config.set_bit_timing(0x001e_000b);
6366
});
6467

6568
// A total of 28 filters are shared between the two CAN instances.

examples/can-loopback.rs

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,11 @@ fn main() -> ! {
2727

2828
// To meet CAN clock accuracy requirements, an external crystal or ceramic
2929
// resonator must be used.
30-
rcc.cfgr
31-
.hse(HSEClock::new(8.mhz(), HSEClockMode::Bypass))
30+
let _clocks = rcc
31+
.cfgr
32+
.hse(HSEClock::new(25.mhz(), HSEClockMode::Bypass))
33+
.sysclk(216.mhz())
34+
.hclk(216.mhz())
3235
.freeze();
3336

3437
let gpioa = dp.GPIOA.split();
@@ -42,9 +45,9 @@ fn main() -> ! {
4245

4346
// Use loopback mode: No pins need to be assigned to peripheral.
4447
can.configure(|config| {
45-
// APB1 (PCLK1): 8MHz, Bit rate: 500Bit/s, Sample Point 87.5%
48+
// APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
4649
// Value was calculated with http://www.bittiming.can-wiki.info/
47-
config.set_bit_timing(0x001c_0000);
50+
config.set_bit_timing(0x001e_000b);
4851
config.set_loopback(true);
4952
config.set_silent(true);
5053
});

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