Merge pull request #108 from santiagoalvarez/master

CAN support

Author: hannobraun

Cargo.toml

@@ -25,6 +25,7 @@ micromath = "1.0.0"
 synopsys-usb-otg = { version = "0.2.3", features = ["cortex-m"], optional = true }
 stm32-fmc = { version = "0.2.0", features = ["sdram"], optional = true }
 rand_core = "0.5.1"
+bxcan = "0.4"
 
 [dependencies.bare-metal]
 version = "0.2.4"
@@ -62,7 +63,7 @@ stm32f730 = ["stm32f7/stm32f730", "device-selected", "usb_hs_phy"]
 stm32f732 = ["stm32f7/stm32f7x2", "device-selected"]
 stm32f733 = ["stm32f7/stm32f7x3", "device-selected", "usb_hs_phy"]
 stm32f745 = ["stm32f7/stm32f745", "device-selected", "fmc"]
-stm32f746 = ["stm32f7/stm32f7x6", "device-selected", "ltdc", "fmc"]
+stm32f746 = ["stm32f7/stm32f7x6", "device-selected", "ltdc", "fmc", "has-can"]
 stm32f756 = ["stm32f7/stm32f7x6", "device-selected", "ltdc", "fmc"]
 stm32f765 = ["stm32f7/stm32f765", "device-selected", "fmc"]
 stm32f767 = ["stm32f7/stm32f7x7", "device-selected", "ltdc", "fmc"]
@@ -74,6 +75,8 @@ stm32f779 = ["stm32f7/stm32f7x9", "device-selected", "ltdc", "fmc"]
 usb_fs = ["synopsys-usb-otg", "synopsys-usb-otg/fs"]
 usb_hs = ["synopsys-usb-otg", "synopsys-usb-otg/hs"]
 
+has-can = []
+
 [profile.dev]
 incremental = false
 codegen-units = 1
@@ -132,4 +135,12 @@ name = "rng"
 
 [[example]]
 name = "stm32f7disco-qspi-flash"
-required-features = ["stm32f746", "rt"]
+required-features = ["stm32f746", "rt"]
+
+[[example]]
+name = "can-echo"
+required-features = ["has-can"]
+
+[[example]]
+name = "can-loopback"
+required-features = ["has-can"]

examples/can-echo.rs

@@ -0,0 +1,94 @@
+//! Simple CAN example.
+//! Requires a transceiver connected to PA11, PA12 (CAN1) or PB5 PB6 (CAN2).
+
+#![no_main]
+#![no_std]
+
+use panic_halt as _;
+
+use bxcan::filter::Mask32;
+use cortex_m_rt::entry;
+use nb::block;
+use stm32f7xx_hal::{
+    can::Can,
+    pac,
+    prelude::*,
+    rcc::{HSEClock, HSEClockMode},
+};
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+
+    let mut rcc = dp.RCC.constrain();
+
+    // To meet CAN clock accuracy requirements an external crystal or ceramic
+    // resonator must be used. The blue pill has a 8MHz external crystal.
+    // Other boards might have a crystal with another frequency or none at all.
+    let _clocks = rcc
+        .cfgr
+        .hse(HSEClock::new(25.mhz(), HSEClockMode::Bypass))
+        .sysclk(216.mhz())
+        .hclk(216.mhz())
+        .freeze();
+
+    let gpioa = dp.GPIOA.split();
+    let gpiob = dp.GPIOB.split();
+
+    let mut can1 = {
+        let rx = gpioa.pa11.into_alternate_af9();
+        let tx = gpioa.pa12.into_alternate_af9();
+
+        let can = Can::new(dp.CAN1, &mut rcc.apb1, (tx, rx));
+        bxcan::Can::new(can)
+    };
+    can1.configure(|config| {
+        // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
+        // Value was calculated with http://www.bittiming.can-wiki.info/
+        config.set_bit_timing(0x001e_000b);
+    });
+
+    // Configure filters so that can frames can be received.
+    let mut filters = can1.modify_filters();
+    filters.enable_bank(0, Mask32::accept_all());
+
+    let _can2 = {
+        let rx = gpiob.pb5.into_alternate_af9();
+        let tx = gpiob.pb6.into_alternate_af9();
+
+        let can = Can::new(dp.CAN2, &mut rcc.apb1, (tx, rx));
+
+        let mut can2 = bxcan::Can::new(can);
+        can2.configure(|config| {
+            // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
+            // Value was calculated with http://www.bittiming.can-wiki.info/
+            config.set_bit_timing(0x001e_000b);
+        });
+
+        // A total of 28 filters are shared between the two CAN instances.
+        // Split them equally between CAN1 and CAN2.
+        filters.set_split(14);
+        let mut slave_filters = filters.slave_filters();
+        slave_filters.enable_bank(14, Mask32::accept_all());
+        can2
+    };
+
+    // Drop filters to leave filter configuraiton mode.
+    drop(filters);
+
+    // Select the interface.
+    let mut can = can1;
+    //let mut can = can2;
+
+    // Split the peripheral into transmitter and receiver parts.
+    block!(can.enable()).unwrap();
+
+    // Echo back received packages in sequence.
+    // See the `can-rtfm` example for an echo implementation that adheres to
+    // correct frame ordering based on the transfer id.
+    loop {
+        if let Ok(frame) = block!(can.receive()) {
+            block!(can.transmit(&frame)).unwrap();
+        }
+    }
+}

examples/can-loopback.rs

@@ -0,0 +1,123 @@
+//! Showcases advanced CAN filter capabilities.
+//! Does not require additional transceiver hardware.
+
+#![no_main]
+#![no_std]
+
+use bxcan::{
+    filter::{ListEntry16, ListEntry32, Mask16},
+    ExtendedId, Frame, StandardId,
+};
+use panic_halt as _;
+
+use cortex_m_rt::entry;
+use nb::block;
+use stm32f7xx_hal::{
+    can::Can,
+    pac,
+    prelude::*,
+    rcc::{HSEClock, HSEClockMode},
+};
+
+#[entry]
+fn main() -> ! {
+    let dp = pac::Peripherals::take().unwrap();
+
+    let mut rcc = dp.RCC.constrain();
+
+    // To meet CAN clock accuracy requirements, an external crystal or ceramic
+    // resonator must be used.
+    let _clocks = rcc
+        .cfgr
+        .hse(HSEClock::new(25.mhz(), HSEClockMode::Bypass))
+        .sysclk(216.mhz())
+        .hclk(216.mhz())
+        .freeze();
+
+    let gpioa = dp.GPIOA.split();
+
+    let rx = gpioa.pa11.into_alternate_af9();
+    let tx = gpioa.pa12.into_alternate_af9();
+
+    let can = Can::new(dp.CAN1, &mut rcc.apb1, (tx, rx));
+
+    let mut can = bxcan::Can::new(can);
+
+    // Use loopback mode: No pins need to be assigned to peripheral.
+    can.configure(|config| {
+        // APB1 (PCLK1): 130MHz, Bit rate: 512kBit/s, Sample Point 87.5%
+        // Value was calculated with http://www.bittiming.can-wiki.info/
+        config.set_bit_timing(0x001e_000b);
+        config.set_loopback(true);
+        config.set_silent(true);
+    });
+
+    let mut filters = can.modify_filters();
+    assert!(filters.num_banks() > 3);
+
+    // The order of the added filters is important: it must match configuration
+    // of the `split_filters_advanced()` method.
+
+    // 2x 11bit id + mask filter bank: Matches 0, 1, 2
+    // TODO: Make this accept also ID 2
+    filters.enable_bank(
+        0,
+        [
+            // accepts 0 and 1
+            Mask16::frames_with_std_id(StandardId::new(0).unwrap(), StandardId::new(1).unwrap()),
+            // accepts 0 and 2
+            Mask16::frames_with_std_id(StandardId::new(0).unwrap(), StandardId::new(2).unwrap()),
+        ],
+    );
+
+    // 2x 29bit id filter bank: Matches 4, 5
+    filters.enable_bank(
+        1,
+        [
+            ListEntry32::data_frames_with_id(ExtendedId::new(4).unwrap()),
+            ListEntry32::data_frames_with_id(ExtendedId::new(5).unwrap()),
+        ],
+    );
+
+    // 4x 11bit id filter bank: Matches 8, 9, 10, 11
+    filters.enable_bank(
+        2,
+        [
+            ListEntry16::data_frames_with_id(StandardId::new(8).unwrap()),
+            ListEntry16::data_frames_with_id(StandardId::new(9).unwrap()),
+            ListEntry16::data_frames_with_id(StandardId::new(10).unwrap()),
+            ListEntry16::data_frames_with_id(StandardId::new(11).unwrap()),
+        ],
+    );
+
+    // Enable filters.
+    drop(filters);
+
+    // Sync to the bus and start normal operation.
+    block!(can.enable()).ok();
+
+    // Some messages shall pass the filters.
+    for &id in &[0, 1, 2, 8, 9, 10, 11] {
+        let frame_tx = Frame::new_data(StandardId::new(id).unwrap(), [id as u8]);
+        block!(can.transmit(&frame_tx)).unwrap();
+        let frame_rx = block!(can.receive()).unwrap();
+        assert_eq!(frame_tx, frame_rx);
+    }
+    for &id in &[4, 5] {
+        let frame_tx = Frame::new_data(ExtendedId::new(id).unwrap(), [id as u8]);
+        block!(can.transmit(&frame_tx)).unwrap();
+        let frame_rx = block!(can.receive()).unwrap();
+        assert_eq!(frame_tx, frame_rx);
+    }
+
+    // Some messages shall not be received.
+    for &id in &[3, 6, 7, 12] {
+        let frame_tx = Frame::new_data(ExtendedId::new(id).unwrap(), [id as u8]);
+        block!(can.transmit(&frame_tx)).unwrap();
+        while !can.is_transmitter_idle() {}
+
+        assert!(can.receive().is_err());
+    }
+
+    loop {}
+}

examples/rng.rs

@@ -17,6 +17,6 @@ fn main() -> ! {
     let val = rng.get_rand().unwrap();
     hprintln!("random value {}", val).unwrap();
     loop {
-        core::sync::atomic::spin_loop_hint();
+        core::hint::spin_loop();
     }
 }

src/can.rs

@@ -0,0 +1,90 @@
+//! # Controller Area Network (CAN) Interface
+//!
+//! ## Alternate function remapping
+//!
+//! TX: Alternate Push-Pull Output
+//! RX: Alternate AF9 Alternate
+//!
+//! ### CAN1
+//!
+//! | Function | NoRemap | Remap |
+//! |----------|---------|-------|
+//! | TX       | PA12    | PB9   |
+//! | RX       | PA11    | PB8   |
+//!
+//! ### CAN2
+//!
+//! | Function | NoRemap | Remap |
+//! |----------|---------|-------|
+//! | TX       | PB6     | PB13  |
+//! | RX       | PB5     | PB12  |
+
+use crate::gpio::gpiob::{PB12, PB13, PB5, PB6, PB8, PB9};
+use crate::gpio::{
+    gpioa::{PA11, PA12},
+    Alternate, AF9,
+};
+use crate::pac::CAN1;
+use crate::pac::CAN2;
+use crate::rcc::APB1;
+
+mod sealed {
+    pub trait Sealed {}
+}
+
+pub trait Pins: sealed::Sealed {
+    type Instance;
+}
+
+impl sealed::Sealed for (PA12<Alternate<AF9>>, PA11<Alternate<AF9>>) {}
+impl Pins for (PA12<Alternate<AF9>>, PA11<Alternate<AF9>>) {
+    type Instance = CAN1;
+}
+
+impl sealed::Sealed for (PB9<Alternate<AF9>>, PB8<Alternate<AF9>>) {}
+impl Pins for (PB9<Alternate<AF9>>, PB8<Alternate<AF9>>) {
+    type Instance = CAN1;
+}
+
+impl sealed::Sealed for (PB6<Alternate<AF9>>, PB5<Alternate<AF9>>) {}
+impl Pins for (PB6<Alternate<AF9>>, PB5<Alternate<AF9>>) {
+    type Instance = CAN2;
+}
+
+impl sealed::Sealed for (PB13<Alternate<AF9>>, PB12<Alternate<AF9>>) {}
+impl Pins for (PB13<Alternate<AF9>>, PB12<Alternate<AF9>>) {
+    type Instance = CAN2;
+}
+
+/// Interface to the CAN peripheral.
+pub struct Can<Instance> {
+    _peripheral: Instance,
+}
+
+impl<Instance> Can<Instance>
+where
+    Instance: crate::rcc::Enable<Bus = APB1>,
+{
+    /// Creates a CAN interaface.
+    pub fn new<P>(can: Instance, apb: &mut APB1, _pins: P) -> Can<Instance>
+    where
+        P: Pins<Instance = Instance>,
+    {
+        Instance::enable(apb);
+        Can { _peripheral: can }
+    }
+}
+
+unsafe impl bxcan::Instance for Can<CAN1> {
+    const REGISTERS: *mut bxcan::RegisterBlock = CAN1::ptr() as *mut _;
+}
+
+unsafe impl bxcan::Instance for Can<CAN2> {
+    const REGISTERS: *mut bxcan::RegisterBlock = CAN2::ptr() as *mut _;
+}
+
+unsafe impl bxcan::FilterOwner for Can<CAN1> {
+    const NUM_FILTER_BANKS: u8 = 28;
+}
+
+unsafe impl bxcan::MasterInstance for Can<CAN1> {}

src/lib.rs

@@ -71,6 +71,9 @@ pub use stm32f7::stm32f7x9 as pac;
 #[cfg(feature = "rt")]
 pub use crate::pac::interrupt;
 
+#[cfg(all(feature = "device-selected", feature = "has-can"))]
+pub mod can;
+
 #[cfg(feature = "device-selected")]
 pub mod delay;
 

src/rcc.rs

@@ -996,6 +996,12 @@ bus! {
     DMA2D => (AHB1, dma2den, dma2drst),
 }
 
+#[cfg(feature = "has-can")]
+bus! {
+    CAN1 => (APB1, can1en, can1rst),
+    CAN2 => (APB1, can2en, can2rst),
+}
+
 #[cfg(test)]
 mod tests {
     use super::{FreqRequest, CFGR};