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Commit 107730c

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Add delay for voltage scaler bridge initialization
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+10
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src/comparator.rs

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ use crate::gpio::*;
88
use crate::rcc::Rcc;
99
use crate::stm32::comp::{COMP1_CSR, COMP2_CSR};
1010
use crate::stm32::{COMP, EXTI};
11+
use crate::time::Hertz;
1112

1213
pub struct COMP1 {
1314
_rb: PhantomData<()>,
@@ -231,6 +232,7 @@ dac_input!(COMP2, dac::Channel2<dac::Enabled>, 0b0101);
231232

232233
pub struct Comparator<C> {
233234
regs: C,
235+
pclk: Hertz,
234236
}
235237

236238
pub trait ComparatorExt<COMP> {
@@ -262,6 +264,9 @@ macro_rules! comparator_ext {
262264
) {
263265
positive_input.setup(&self.regs);
264266
negative_input.setup(&self.regs);
267+
// Delay for scaler voltage bridge initialization for certain negative inputs
268+
let voltage_scaler_delay = self.pclk.0 / (1_000_000 / 200); // 200us
269+
cortex_m::asm::delay(voltage_scaler_delay);
265270
self.regs.csr().modify(|_, w| unsafe {
266271
w.hyst()
267272
.bits(config.hysteresis as u8)
@@ -272,7 +277,6 @@ macro_rules! comparator_ext {
272277
.winout()
273278
.bit(config.output_xor)
274279
});
275-
// TODO: Delay for comp scaler bridge voltage stabilization?
276280
}
277281

278282
fn output(&self) -> bool {
@@ -281,7 +285,6 @@ macro_rules! comparator_ext {
281285

282286
fn enable(&self) {
283287
self.regs.csr().modify(|_, w| w.en().set_bit());
284-
// TODO: Startup delay?
285288
}
286289

287290
fn disable(&self) {
@@ -425,12 +428,17 @@ pub fn split(_comp: COMP, rcc: &mut Rcc) -> (Comparator<COMP1>, Comparator<COMP2
425428
rcc.rb.apbrstr2.modify(|_, w| w.syscfgrst().set_bit());
426429
rcc.rb.apbrstr2.modify(|_, w| w.syscfgrst().clear_bit());
427430

431+
// Used to calculate delays for initialization
432+
let pclk = rcc.clocks.apb_clk;
433+
428434
(
429435
Comparator {
430436
regs: COMP1 { _rb: PhantomData },
437+
pclk,
431438
},
432439
Comparator {
433440
regs: COMP2 { _rb: PhantomData },
441+
pclk,
434442
},
435443
)
436444
}

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