rcc refactoring

Author: dotcypress

src/analog/adc.rs

@@ -113,7 +113,8 @@ pub struct CalibrationFactor(pub u8);
 impl Adc {
     pub fn new(adc: ADC, rcc: &mut Rcc) -> Self {
         // Enable ADC clocks
-        rcc.rb.apbenr2.modify(|_, w| w.adcen().set_bit());
+        rcc.enable_adc();
+
         adc.cr.modify(|_, w| w.advregen().set_bit());
 
         Self {

src/crc.rs

@@ -31,11 +31,7 @@ pub trait CrcExt {
 
 impl CrcExt for CRC {
     fn constrain(self, rcc: &mut Rcc) -> Config {
-        // Enable power to CRC unit
-        rcc.rb.ahbenr.modify(|_, w| w.crcen().set_bit());
-        // Reset CRC unit
-        rcc.rb.ahbrstr.modify(|_, w| w.crcrst().set_bit());
-        rcc.rb.ahbrstr.modify(|_, w| w.crcrst().clear_bit());
+        rcc.enable_crc();
 
         // Default values
         Config {

src/flash/mod.rs

@@ -189,7 +189,7 @@ impl WriteErase for UnlockedFlash {
 
         let mut chunks = aligned_data.chunks_exact(mem::size_of::<Self::NativeType>());
 
-        while let Some(exact_chunk) = chunks.next() {
+        for exact_chunk in &mut chunks {
             // Write chunks
             let native = &[Self::NativeType::from_ne_bytes(
                 exact_chunk.try_into().unwrap(),

src/gpio.rs

@@ -177,30 +177,35 @@ macro_rules! gpio {
                     _mode: PhantomData<MODE>,
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<PullDown>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<PullDown>> {
                         self.into_pull_down_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<PullUp>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<PullUp>> {
                         self.into_pull_up_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Input<Floating>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Input<Floating>> {
                         self.into_floating_input()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Output<OpenDrain>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Output<OpenDrain>> {
                         self.into_open_drain_output()
                     }
                 }
 
+                #[allow(clippy::from_over_into)]
                 impl Into<$PXi<Output<PushPull>>> for $PXi<DefaultMode> {
                     fn into(self) -> $PXi<Output<PushPull>> {
                         self.into_push_pull_output()

src/rcc/mod.rs

@@ -315,6 +315,16 @@ impl Rcc {
     pub(crate) fn enable_power_control(&self) {
         self.rb.apbenr1.modify(|_, w| w.pwren().set_bit());
     }
+
+    pub(crate) fn enable_adc(&self) {
+        self.rb.apbenr2.modify(|_, w| w.adcen().set_bit());
+    }
+
+    pub(crate) fn enable_crc(&self) {
+        self.rb.ahbenr.modify(|_, w| w.crcen().set_bit());
+        self.rb.ahbrstr.modify(|_, w| w.crcrst().set_bit());
+        self.rb.ahbrstr.modify(|_, w| w.crcrst().clear_bit());
+    }
 }
 
 /// Extension trait that constrains the `RCC` peripheral

src/serial/usart.rs

@@ -326,7 +326,6 @@ macro_rules! uart_shared {
                 });
             }
         }
-
     }
 }
 

src/time.rs

@@ -217,6 +217,12 @@ impl Add for MicroSecond {
     }
 }
 
+impl From<Second> for MicroSecond {
+    fn from(period: Second) -> MicroSecond {
+        MicroSecond(period.0 * 1_000_000)
+    }
+}
+
 impl From<Hertz> for MicroSecond {
     fn from(freq: Hertz) -> MicroSecond {
         assert!(freq.0 <= 1_000_000);