adc refactoring

Author: dotcypress

examples/adc_ext_trig_double_dma_serial.rs

@@ -15,6 +15,7 @@ extern crate panic_halt;
 extern crate stm32g0;
 extern crate stm32g0xx_hal as hal;
 
+use hal::analog::adc;
 use hal::prelude::*;
 use hal::serial::*;
 use hal::stm32;
@@ -62,24 +63,22 @@ unsafe fn DMA_CHANNEL1() {
     // Address is in byte, value in 2Bytes, this is why second dma buffer ist added with BUFFER_SIZE
     // and not BUFFER_SIZE/2
 
-    unsafe {
-        let dma = &(*stm32g0::stm32g031::DMA::ptr());
-        let htif1 = dma.isr.read().htif1().bit();
-        let tcif1 = dma.isr.read().tcif1().bit();
-        // set the global clear bit of DMA channel1
-        dma.ifcr.write(|w| w.cgif1().set_bit());
-
-        dma_ch.ch2.disable();
-        dma_ch.ch2.set_transfer_length(BUFFER_SIZE as u16);
-        if htif1 == true {
-            dma_ch.ch2.set_memory_address(tx_dma_buf_first_addr, true);
-            dma_ch.ch2.enable();
-            // hprintln!("DMA_CHANNEL1 half transfer compleated {:?} {:?}", htif1, tx_dma_buf_first_addr).unwrap();
-        } else if tcif1 == true {
-            dma_ch.ch2.set_memory_address(tx_dma_buf_second_addr, true);
-            dma_ch.ch2.enable();
-            // hprintln!("DMA_CHANNEL1 transfer compleated {:?}  {:?}", tcif1, tx_dma_buf_second_addr).unwrap();
-        }
+    let dma = &(*stm32g0::stm32g031::DMA::ptr());
+    let htif1 = dma.isr.read().htif1().bit();
+    let tcif1 = dma.isr.read().tcif1().bit();
+    // set the global clear bit of DMA channel1
+    dma.ifcr.write(|w| w.cgif1().set_bit());
+
+    dma_ch.ch2.disable();
+    dma_ch.ch2.set_transfer_length(BUFFER_SIZE as u16);
+    if htif1 == true {
+        dma_ch.ch2.set_memory_address(tx_dma_buf_first_addr, true);
+        dma_ch.ch2.enable();
+        // hprintln!("DMA_CHANNEL1 half transfer compleated {:?} {:?}", htif1, tx_dma_buf_first_addr).unwrap();
+    } else if tcif1 == true {
+        dma_ch.ch2.set_memory_address(tx_dma_buf_second_addr, true);
+        dma_ch.ch2.enable();
+        // hprintln!("DMA_CHANNEL1 transfer compleated {:?}  {:?}", tcif1, tx_dma_buf_second_addr).unwrap();
     }
 }
 
@@ -167,9 +166,9 @@ fn main() -> ! {
     let u = u_raw.saturating_sub(32) as f32 / 4_096_f32 * 3.3;
     hprintln!("u: {:.4} V ", u).unwrap();
 
-    adc.set_oversamling_ratio(3);
+    adc.set_oversamling_ratio(adc::OversamplingRatio::X_16);
     adc.set_oversamling_shift(4);
-    adc.oversamling_enable();
+    adc.oversamling_enable(true);
     adc.prepare_injected(&mut pa3, InjTrigSource::TRG_2);
     adc.start_injected();
 

src/analog/adc.rs

@@ -46,6 +46,19 @@ pub enum SampleTime {
     T_160 = 0b111,
 }
 
+// ADC Oversampling ratio
+#[derive(Copy, Clone, PartialEq)]
+pub enum OversamplingRatio {
+    X_2 = 0b000,
+    X_4 = 0b001,
+    X_8 = 0b010,
+    X_16 = 0b011,
+    X_32 = 0b100,
+    X_64 = 0b101,
+    X_128 = 0b110,
+    X_256 = 0b111,
+}
+
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 pub enum ClockSource {
     Pclk(PclkDiv),
@@ -111,6 +124,7 @@ impl Adc {
         }
     }
 
+    /// Sets ADC source
     pub fn set_clock_source(&mut self, clock_source: ClockSource) {
         match clock_source {
             ClockSource::Pclk(div) => self
@@ -176,22 +190,6 @@ impl Adc {
         self.precision = precision;
     }
 
-    fn power_up(&mut self) {
-        self.rb.isr.modify(|_, w| w.adrdy().set_bit());
-        self.rb.cr.modify(|_, w| w.aden().set_bit());
-        while self.rb.isr.read().adrdy().bit_is_clear() {}
-    }
-
-    fn power_down(&mut self) {
-        self.rb.cr.modify(|_, w| w.addis().set_bit());
-        self.rb.isr.modify(|_, w| w.adrdy().set_bit());
-        while self.rb.cr.read().aden().bit_is_set() {}
-    }
-
-    pub fn release(self) -> ADC {
-        self.rb
-    }
-
     /// The nuber of bits, the oversampling result is shifted in bits at the end of oversampling
     pub fn set_oversamling_shift(&mut self, nrbits: u8) {
         self.rb
@@ -200,23 +198,14 @@ impl Adc {
     }
 
     /// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
-    /// 000: 2x
-    /// 001: 4x
-    /// 010: 8x
-    /// 011: 16x
-    /// 100: 32x
-    /// 101: 64x
-    /// 110: 128x
-    /// 111: 256x
-
-    pub fn set_oversamling_ratio(&mut self, multyply: u8) {
+    pub fn set_oversamling_ratio(&mut self, ratio: OversamplingRatio) {
         self.rb
             .cfgr2
-            .modify(|_, w| unsafe { w.ovsr().bits(multyply) });
+            .modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
     }
 
-    pub fn oversamling_enable(&mut self) {
-        self.rb.cfgr2.modify(|_, w| w.ovse().set_bit());
+    pub fn oversamling_enable(&mut self, enable: bool) {
+        self.rb.cfgr2.modify(|_, w| w.ovse().bit(enable));
     }
 
     pub fn start_injected(&mut self) {
@@ -233,6 +222,22 @@ impl Adc {
         // maybe self.rb.cr.adstp().set_bit() must be performed before interrupt is disabled + wait abortion
         self.rb.ier.modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
     }
+
+    pub fn release(self) -> ADC {
+        self.rb
+    }
+
+    fn power_up(&mut self) {
+        self.rb.isr.modify(|_, w| w.adrdy().set_bit());
+        self.rb.cr.modify(|_, w| w.aden().set_bit());
+        while self.rb.isr.read().adrdy().bit_is_clear() {}
+    }
+
+    fn power_down(&mut self) {
+        self.rb.cr.modify(|_, w| w.addis().set_bit());
+        self.rb.isr.modify(|_, w| w.adrdy().set_bit());
+        while self.rb.cr.read().aden().bit_is_set() {}
+    }
 }
 
 pub trait AdcExt {