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dotcypressdotcypress
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gpio alternate mode sequence
1 parent f06030c commit 2344777

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8 files changed

+22
-29
lines changed

8 files changed

+22
-29
lines changed

‎examples/stopwatch.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ fn main() -> ! {
2828

2929
#[cfg(feature = "stm32g0x1")]
3030
let mut stopwatch = dp.TIM2.stopwatch(&mut rcc);
31-
#[cfg(feature = "stm32g0x0")] // TODO: not tested yet with TIM3
31+
#[cfg(feature = "stm32g0x0")]
3232
let mut stopwatch = dp.TIM3.stopwatch(&mut rcc);
3333

3434
let elapsed_us = stopwatch.trace(|| {

‎src/analog/comparator.rs

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -102,16 +102,6 @@ pub enum Hysteresis {
102102
High = 0b11,
103103
}
104104

105-
// TODO
106-
// pub enum Blanking {
107-
// None,
108-
// Tim1Oc4(),
109-
// Tim1Oc5(),
110-
// Tim2Oc3(),
111-
// Tim3Oc3(),
112-
// Tim15Oc2()<
113-
// }
114-
115105
#[derive(Copy, Clone, Eq, PartialEq)]
116106
pub enum PowerMode {
117107
HighSpeed = 0b00,

‎src/i2c.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -188,10 +188,6 @@ macro_rules! i2c {
188188
SDA: SDAPin<$I2CX>,
189189
SCL: SCLPin<$I2CX>,
190190
{
191-
192-
sda.setup();
193-
scl.setup();
194-
195191
// Enable clock for I2C
196192
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().set_bit());
197193

@@ -206,6 +202,10 @@ macro_rules! i2c {
206202
let timing_bits = config.timing_bits(rcc.clocks.apb_clk);
207203
i2c.timingr.write(|w| unsafe { w.bits(timing_bits) });
208204

205+
// Enable pins
206+
sda.setup();
207+
scl.setup();
208+
209209
// Enable the I2C processing
210210
i2c.cr1.modify(|_, w| unsafe {
211211
w.pe()

‎src/rcc/clockout.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,6 @@ pub trait LSCOExt {
3030

3131
impl LSCOExt for LscoPin {
3232
fn lsco(self, src: LSCOSrc, rcc: &mut Rcc) -> Lsco {
33-
self.set_alt_mode(AltFunction::AF0);
3433
let src_select_bit = match src {
3534
LSCOSrc::LSE => {
3635
rcc.enable_lse(false);
@@ -42,6 +41,7 @@ impl LSCOExt for LscoPin {
4241
}
4342
};
4443
rcc.unlock_rtc();
44+
self.set_alt_mode(AltFunction::AF0);
4545
rcc.rb.bdcr.modify(|_, w| w.lscosel().bit(src_select_bit));
4646
Lsco { pin: self }
4747
}
@@ -78,8 +78,6 @@ macro_rules! mco {
7878
$(
7979
impl MCOExt<$PIN> for $PIN {
8080
fn mco(self, src: MCOSrc, psc: Prescaler, rcc: &mut Rcc) -> Mco<$PIN> {
81-
self.set_alt_mode(AltFunction::AF0);
82-
8381
let psc_bits = match psc {
8482
Prescaler::NotDivided => 0b000,
8583
Prescaler::Div2 => 0b001,
@@ -90,6 +88,7 @@ macro_rules! mco {
9088
Prescaler::Div64 => 0b110,
9189
_ => 0b111,
9290
};
91+
9392
rcc.rb.cfgr.modify(|r, w| unsafe {
9493
w.bits((r.bits() & !(0b111 << 28)) | (psc_bits << 28))
9594
});
@@ -114,6 +113,8 @@ macro_rules! mco {
114113
0b111
115114
},
116115
};
116+
117+
self.set_alt_mode(AltFunction::AF0);
117118
Mco { src_bits, pin: self }
118119
}
119120
}

‎src/serial/usart.rs

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -362,9 +362,6 @@ macro_rules! uart_basic {
362362
TX: TxPin<$USARTX>,
363363
RX: RxPin<$USARTX>,
364364
{
365-
tx.setup();
366-
rx.setup();
367-
368365
// Enable clock for USART
369366
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
370367
let clk = rcc.clocks.apb_clk.0 as u64;
@@ -405,6 +402,10 @@ macro_rules! uart_basic {
405402
.bit(config.swap)
406403
});
407404

405+
// Enable pins
406+
tx.setup();
407+
rx.setup();
408+
408409
// Enable USART
409410
usart.cr1.modify(|_, w| w.ue().set_bit());
410411

@@ -491,9 +492,6 @@ macro_rules! uart_full {
491492
TX: TxPin<$USARTX>,
492493
RX: RxPin<$USARTX>,
493494
{
494-
tx.setup();
495-
rx.setup();
496-
497495
// Enable clock for USART
498496
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
499497

@@ -550,6 +548,9 @@ macro_rules! uart_full {
550548
.bit(config.fifo_enable)
551549
});
552550

551+
tx.setup();
552+
rx.setup();
553+
553554
Ok(Serial {
554555
tx: Tx {
555556
_usart: PhantomData,

‎src/spi.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -117,8 +117,6 @@ macro_rules! spi {
117117
PINS: Pins<$SPIX>,
118118
T: Into<Hertz>
119119
{
120-
pins.setup();
121-
122120
// Enable clock for SPI
123121
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().set_bit());
124122
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().set_bit());
@@ -145,6 +143,9 @@ macro_rules! spi {
145143
w.frxth().set_bit().ds().bits(0b111).ssoe().clear_bit()
146144
});
147145

146+
// Enable pins
147+
pins.setup();
148+
148149
spi.cr1.write(|w| unsafe {
149150
w.cpha()
150151
.bit(mode.phase == Phase::CaptureOnSecondTransition)
@@ -172,7 +173,6 @@ macro_rules! spi {
172173
.set_bit()
173174
});
174175

175-
176176
Spi { spi, pins }
177177
}
178178

‎src/timer/opm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,10 @@ macro_rules! opm {
3737
where
3838
PIN: TimerPin<$TIMX>,
3939
{
40-
pin.setup();
4140
rcc.rb.$apbXenr.modify(|_, w| w.$timXen().set_bit());
4241
rcc.rb.$apbXrstr.modify(|_, w| w.$timXrst().set_bit());
4342
rcc.rb.$apbXrstr.modify(|_, w| w.$timXrst().clear_bit());
43+
pin.setup();
4444
Opm {
4545
rb: tim,
4646
clk: rcc.clocks.apb_tim_clk,

‎src/timer/qei.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@ macro_rules! qei {
4242
$(
4343
impl<PINS> Qei<$TIMX, PINS> where PINS: QeiPins<$TIMX> {
4444
fn $tim(tim: $TIMX, pins: PINS, rcc: &mut Rcc) -> Self {
45-
pins.setup();
4645
// enable and reset peripheral to a clean slate state
4746
rcc.rb.$apbenr.modify(|_, w| w.$timXen().set_bit());
4847
rcc.rb.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
@@ -72,6 +71,8 @@ macro_rules! qei {
7271
.clear_bit()
7372
});
7473

74+
pins.setup();
75+
7576
tim.cr1.write(|w| w.cen().set_bit());
7677
Qei { tim, pins }
7778
}

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