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rblazerblaze
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Update stm32g0 to 0.15.1
1 parent 8f6e6bb commit 249fbba

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8 files changed

+34
-41
lines changed

8 files changed

+34
-41
lines changed

‎Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ nb = "1.0.0"
2121
fugit = "0.3.5"
2222

2323
[dependencies.stm32g0]
24-
version = "0.14.0"
24+
version = "0.15.1"
2525
features = ["rt"]
2626

2727
[dependencies.bare-metal]

‎src/analog/adc.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -362,7 +362,7 @@ where
362362
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
363363

364364
self.rb
365-
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
365+
.chselr0() // set active channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
366366
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
367367
}
368368
}
@@ -415,7 +415,7 @@ where
415415
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
416416

417417
self.rb
418-
.chselr()
418+
.chselr0()
419419
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
420420

421421
self.rb.isr.modify(|_, w| w.eos().set_bit());

‎src/analog/dac.rs

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -106,8 +106,8 @@ macro_rules! dac {
106106
pub fn enable(self) -> $CX<Enabled> {
107107
let dac = unsafe { &(*DAC::ptr()) };
108108

109-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
110-
dac.dac_cr.modify(|_, w| w.$en().set_bit());
109+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
110+
dac.cr.modify(|_, w| w.$en().set_bit());
111111

112112
$CX {
113113
_enabled: PhantomData,
@@ -117,8 +117,8 @@ macro_rules! dac {
117117
pub fn enable_unbuffered(self) -> $CX<EnabledUnbuffered> {
118118
let dac = unsafe { &(*DAC::ptr()) };
119119

120-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
121-
dac.dac_cr.modify(|_, w| w.$en().set_bit());
120+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(2) });
121+
dac.cr.modify(|_, w| w.$en().set_bit());
122122

123123
$CX {
124124
_enabled: PhantomData,
@@ -128,8 +128,8 @@ macro_rules! dac {
128128
pub fn enable_generator(self, config: GeneratorConfig) -> $CX<WaveGenerator> {
129129
let dac = unsafe { &(*DAC::ptr()) };
130130

131-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
132-
dac.dac_cr.modify(|_, w| unsafe {
131+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(1) });
132+
dac.cr.modify(|_, w| unsafe {
133133
w.$wave().bits(config.mode);
134134
w.$ten().set_bit();
135135
w.$mamp().bits(config.amp);
@@ -159,19 +159,19 @@ macro_rules! dac {
159159
T: DelayUs<u32>,
160160
{
161161
let dac = unsafe { &(*DAC::ptr()) };
162-
dac.dac_cr.modify(|_, w| w.$en().clear_bit());
163-
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
164-
dac.dac_cr.modify(|_, w| w.$cen().set_bit());
162+
dac.cr.modify(|_, w| w.$en().clear_bit());
163+
dac.mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
164+
dac.cr.modify(|_, w| w.$cen().set_bit());
165165
let mut trim = 0;
166166
while true {
167-
dac.dac_ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
167+
dac.ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
168168
delay.delay_us(64_u32);
169-
if dac.dac_sr.read().$cal_flag().bit() {
169+
if dac.sr.read().$cal_flag().bit() {
170170
break;
171171
}
172172
trim += 1;
173173
}
174-
dac.dac_cr.modify(|_, w| w.$cen().clear_bit());
174+
dac.cr.modify(|_, w| w.$cen().clear_bit());
175175

176176
$CX {
177177
_enabled: PhantomData,
@@ -181,7 +181,7 @@ macro_rules! dac {
181181
/// Disable the DAC channel
182182
pub fn disable(self) -> $CX<Disabled> {
183183
let dac = unsafe { &(*DAC::ptr()) };
184-
dac.dac_cr.modify(|_, w| unsafe {
184+
dac.cr.modify(|_, w| unsafe {
185185
w.$en().clear_bit().$wave().bits(0).$ten().clear_bit()
186186
});
187187

@@ -209,7 +209,7 @@ macro_rules! dac {
209209
impl $CX<WaveGenerator> {
210210
pub fn trigger(&mut self) {
211211
let dac = unsafe { &(*DAC::ptr()) };
212-
dac.dac_swtrgr.write(|w| { w.$swtrig().set_bit() });
212+
dac.swtrgr.write(|w| { w.$swtrig().set_bit() });
213213
}
214214
}
215215
)+
@@ -239,8 +239,8 @@ dac!(
239239
cal_flag1,
240240
otrim1,
241241
mode1,
242-
dac_dhr12r1,
243-
dac_dor1,
242+
dhr12r1,
243+
dor1,
244244
dacc1dhr,
245245
wave1,
246246
mamp1,
@@ -254,8 +254,8 @@ dac!(
254254
cal_flag2,
255255
otrim2,
256256
mode2,
257-
dac_dhr12r2,
258-
dac_dor2,
257+
dhr12r2,
258+
dor2,
259259
dacc2dhr,
260260
wave2,
261261
mamp2,

‎src/dmamux.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -185,13 +185,13 @@ macro_rules! dma_mux {
185185
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
186186
dma_mux!(
187187
channels: {
188-
C0: (ch0, dmamux_c0cr),
189-
C1: (ch1, dmamux_c1cr),
190-
C2: (ch2, dmamux_c2cr),
191-
C3: (ch3, dmamux_c3cr),
192-
C4: (ch4, dmamux_c4cr),
193-
C5: (ch5, dmamux_c5cr),
194-
C6: (ch6, dmamux_c6cr),
188+
C0: (ch0, c0cr),
189+
C1: (ch1, c1cr),
190+
C2: (ch2, c2cr),
191+
C3: (ch3, c3cr),
192+
C4: (ch4, c4cr),
193+
C5: (ch5, c5cr),
194+
C6: (ch6, c6cr),
195195
},
196196
);
197197

‎src/i2c/blocking.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ macro_rules! i2c {
187187

188188
if config.slave_address_1 > 0 {
189189
i2c.oar1.write(|w| unsafe {
190-
w.oa1_7_1().bits(config.slave_address_1 as u8)
190+
w.oa1().bits(config.slave_address_1)
191191
.oa1mode().bit(config.address_11bits)
192192
.oa1en().set_bit()
193193
});

‎src/spi.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ macro_rules! spi {
169169
// Enable pins
170170
pins.setup();
171171

172-
spi.cr1.write(|w| unsafe {
172+
spi.cr1.write(|w| {
173173
w.cpha()
174174
.bit(mode.phase == Phase::CaptureOnSecondTransition)
175175
.cpol()
@@ -186,12 +186,10 @@ macro_rules! spi {
186186
.set_bit()
187187
.rxonly()
188188
.clear_bit()
189-
.dff()
189+
.crcl()
190190
.clear_bit()
191191
.bidimode()
192192
.clear_bit()
193-
.ssi()
194-
.set_bit()
195193
.spe()
196194
.set_bit()
197195
});

‎src/timer/pwm.rs

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -269,12 +269,7 @@ pwm_advanced_hal! {
269269
TIM17: (Channel1, cc1e: cc1ne, ccmr1_output, oc1pe, oc1m, ccr1, moe),
270270
}
271271

272-
#[cfg(feature = "stm32g070")]
273-
pwm_advanced_hal! {
274-
TIM15: (Channel1, cc1e: cc1ne, ccmr1_output, oc1pe, oc1m1, ccr1, moe),
275-
}
276-
277-
#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
272+
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
278273
pwm_advanced_hal! {
279274
TIM15: (Channel1, cc1e: cc1ne, ccmr1_output, oc1pe, oc1m, ccr1, moe),
280275
}

‎src/watchdog.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ pub struct WindowWatchdog {
8383

8484
impl WindowWatchdog {
8585
pub fn feed(&mut self) {
86-
self.wwdg.cr.write(|w| unsafe { w.t().bits(0xff) });
86+
self.wwdg.cr.write(|w| w.t().bits(0xff));
8787
}
8888

8989
pub fn set_window(&mut self, window: MicroSecond) {
@@ -101,7 +101,7 @@ impl WindowWatchdog {
101101
assert!(window <= 0x40);
102102
self.wwdg
103103
.cfr
104-
.write(|w| unsafe { w.wdgtb().bits(psc).w().bits(window as u8) });
104+
.write(|w| w.wdgtb().bits(psc).w().bits(window as u8));
105105
}
106106

107107
pub fn listen(&mut self) {

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