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UART: add Tx/Rx pin swapping
1 parent e4dc211 commit 3e9b327

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2 files changed

+35
-9
lines changed

2 files changed

+35
-9
lines changed

src/serial/config.rs

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ pub struct BasicConfig {
6060
pub(crate) wordlength: WordLength,
6161
pub(crate) parity: Parity,
6262
pub(crate) stopbits: StopBits,
63+
pub(crate) swap: bool,
6364
}
6465

6566
#[derive(PartialEq, PartialOrd, Clone, Copy)]
@@ -68,6 +69,7 @@ pub struct FullConfig {
6869
pub(crate) wordlength: WordLength,
6970
pub(crate) parity: Parity,
7071
pub(crate) stopbits: StopBits,
72+
pub(crate) swap: bool,
7173
pub(crate) fifo_enable: bool,
7274
pub(crate) tx_fifo_threshold: FifoThreshold,
7375
pub(crate) rx_fifo_threshold: FifoThreshold,
@@ -112,6 +114,14 @@ impl BasicConfig {
112114
self.stopbits = stopbits;
113115
self
114116
}
117+
118+
/// Swap the Tx/Rx pins
119+
///
120+
/// The peripheral will transmit on the pin given as the `rx` argument.
121+
pub fn swap_pins(mut self) -> Self {
122+
self.swap = true;
123+
self
124+
}
115125
}
116126

117127
impl FullConfig {
@@ -150,6 +160,14 @@ impl FullConfig {
150160
self
151161
}
152162

163+
/// Swap the Tx/Rx pins
164+
///
165+
/// The peripheral will transmit on the pin given as the `rx` argument.
166+
pub fn swap_pins(mut self) -> Self {
167+
self.swap = true;
168+
self
169+
}
170+
153171
pub fn fifo_enable(mut self) -> Self {
154172
self.fifo_enable = true;
155173
self
@@ -194,6 +212,7 @@ impl Default for BasicConfig {
194212
wordlength: WordLength::DataBits8,
195213
parity: Parity::ParityNone,
196214
stopbits: StopBits::STOP1,
215+
swap: false,
197216
}
198217
}
199218
}
@@ -206,6 +225,7 @@ impl Default for FullConfig {
206225
wordlength: WordLength::DataBits8,
207226
parity: Parity::ParityNone,
208227
stopbits: StopBits::STOP1,
228+
swap: false,
209229
fifo_enable: false,
210230
tx_fifo_threshold: FifoThreshold::FIFO_8_BYTES,
211231
rx_fifo_threshold: FifoThreshold::FIFO_8_BYTES,

src/serial/usart.rs

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -380,12 +380,15 @@ macro_rules! uart_basic {
380380
.bit(config.parity == Parity::ParityOdd)
381381
});
382382
usart.cr2.write(|w| unsafe {
383-
w.stop().bits(match config.stopbits {
384-
StopBits::STOP1 => 0b00,
385-
StopBits::STOP0P5 => 0b01,
386-
StopBits::STOP2 => 0b10,
387-
StopBits::STOP1P5 => 0b11,
388-
})
383+
w.stop()
384+
.bits(match config.stopbits {
385+
StopBits::STOP1 => 0b00,
386+
StopBits::STOP0P5 => 0b01,
387+
StopBits::STOP2 => 0b10,
388+
StopBits::STOP1P5 => 0b11,
389+
})
390+
.swap()
391+
.bit(config.swap)
389392
});
390393

391394
// Enable USART
@@ -490,9 +493,12 @@ macro_rules! uart_full {
490493
usart.cr2.reset();
491494
usart.cr3.reset();
492495

493-
usart
494-
.cr2
495-
.write(|w| unsafe { w.stop().bits(config.stopbits.bits()) });
496+
usart.cr2.write(|w| unsafe {
497+
w.stop()
498+
.bits(config.stopbits.bits())
499+
.swap()
500+
.bit(config.swap)
501+
});
496502

497503
if let Some(timeout) = config.receiver_timeout {
498504
usart.cr1.write(|w| w.rtoie().set_bit());

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