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oldsheep68oldsheep68
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Revert "cargo fmt run"
This reverts commit 5ed7574.
1 parent 5ed7574 commit 5039814

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2 files changed

+79
-67
lines changed

2 files changed

+79
-67
lines changed

‎examples/adc_ext_trig_double_dma_serial.rs

Lines changed: 38 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -9,28 +9,31 @@
99

1010
extern crate cortex_m;
1111
extern crate cortex_m_rt as rt;
12-
use cortex_m_semihosting::hprintln;
12+
use cortex_m_semihosting::{ hprintln};
1313

1414
extern crate nb;
1515
extern crate panic_halt;
16-
extern crate stm32g0;
1716
extern crate stm32g0xx_hal as hal;
17+
extern crate stm32g0;
18+
1819

1920
use hal::prelude::*;
20-
use hal::serial::*;
2121
use hal::stm32;
22+
use hal::serial::*;
2223
use rt::entry;
2324

24-
use core::cell::RefCell;
25-
use cortex_m::interrupt::Mutex;
25+
use core::cell::{RefCell};
26+
use cortex_m::{ interrupt::Mutex};
2627

27-
use crate::hal::stm32::{interrupt, Interrupt};
28-
use hal::analog::adc::{InjTrigSource, Precision, SampleTime}; //, VTemp
28+
use crate::hal::{
29+
stm32::{interrupt, Interrupt},
30+
};
31+
use hal::analog::adc::{Precision, SampleTime, InjTrigSource}; //, VTemp
2932

3033
use hal::dma::{self, Channel, Target};
3134

32-
use crate::hal::analog::adc::DmaMode;
3335
use crate::hal::analog::adc::InjectMode;
36+
use crate::hal::analog::adc::DmaMode;
3437

3538
// Make dma globally available
3639
static G_DMA: Mutex<RefCell<Option<hal::dma::Channels>>> = Mutex::new(RefCell::new(None));
@@ -57,12 +60,13 @@ fn DMA_CHANNEL1() {
5760
G_DMA_BUFFER_ADDR.borrow(cs).replace(None).unwrap()
5861
})
5962
});
60-
63+
6164
let tx_dma_buf_first_addr: u32 = *dma_buf_addr;
62-
let tx_dma_buf_second_addr: u32 = *dma_buf_addr + (BUFFER_SIZE) as u32;
63-
// Address is in byte, value in 2Bytes, this is why second dma buffer ist added with BUFFER_SIZE
65+
let tx_dma_buf_second_addr: u32 = *dma_buf_addr + (BUFFER_SIZE) as u32;
66+
// Address is in byte, value in 2Bytes, this is why second dma buffer ist added with BUFFER_SIZE
6467
// and not BUFFER_SIZE/2
65-
68+
69+
6670
unsafe {
6771
let dma = &(*stm32g0::stm32g031::DMA::ptr());
6872
let htif1 = dma.isr.read().htif1().bit();
@@ -96,16 +100,17 @@ fn main() -> ! {
96100
let usart1 = dp
97101
.USART1
98102
.usart(
99-
gpioa.pa9, // TX: pa9, => CN3 Pin-D5
100-
gpioa.pa10, // RX: pa10, => CN3 Pin-D4
101-
FullConfig::default().baudrate(460800.bps()).fifo_enable(), // enable fifo, so that dma can fill it fast, otherwise it may not finish before ch1 is requested again
103+
gpioa.pa9, // TX: pa9, => CN3 Pin-D5
104+
gpioa.pa10, // RX: pa10, => CN3 Pin-D4
105+
FullConfig::default().baudrate(460800.bps())
106+
.fifo_enable(), // enable fifo, so that dma can fill it fast, otherwise it may not finish before ch1 is requested again
102107
&mut rcc,
103108
)
104109
.unwrap();
105110

106111
// DMA example
107112
//==================================================
108-
let adc_buffer1: [u16; BUFFER_SIZE as usize] = [0; BUFFER_SIZE as usize];
113+
let adc_buffer1: [u16; BUFFER_SIZE as usize] = [0;BUFFER_SIZE as usize];
109114

110115
let mut dma = dp.DMA.split(&mut rcc, dp.DMAMUX);
111116

@@ -117,18 +122,16 @@ fn main() -> ! {
117122
dma.ch1.set_word_size(dma::WordSize::BITS16);
118123
dma.ch1.set_direction(dma::Direction::FromPeripheral);
119124
dma.ch1.set_memory_address(adc_buffer1_addr, true);
120-
dma.ch1
121-
.set_peripheral_address(adc_data_register_addr, false);
125+
dma.ch1.set_peripheral_address(adc_data_register_addr, false);
122126
dma.ch1.set_transfer_length(adc_buffer1.len() as u16);
123-
127+
124128
hprintln!("adc_data_register_addr {:?}", adc_buffer1_addr).unwrap(); // will output addr in dec
125-
// in gdb read the data bytes with: x /32xh 0x??????? (last is addr in hex)
126-
// or put addr in dec format: x /32xh 536878092
127-
// https://sourceware.org/gdb/current/onlinedocs/gdb/Memory.html
129+
// in gdb read the data bytes with: x /32xh 0x??????? (last is addr in hex)
130+
// or put addr in dec format: x /32xh 536878092
131+
// https://sourceware.org/gdb/current/onlinedocs/gdb/Memory.html
128132

129133
// dma ch1 reads from ADC register into memory
130-
dma.ch1
131-
.select_peripheral(stm32g0xx_hal::dmamux::DmaMuxIndex::ADC);
134+
dma.ch1.select_peripheral(stm32g0xx_hal::dmamux::DmaMuxIndex::ADC);
132135
// The dma continuesly fills the buffer, when its full, it starts over again
133136
dma.ch1.set_circular_mode(true);
134137

@@ -153,9 +156,9 @@ fn main() -> ! {
153156
dma.ch1.enable();
154157

155158
cortex_m::interrupt::free(|cs| *G_DMA.borrow(cs).borrow_mut() = Some(dma));
156-
cortex_m::interrupt::free(|cs| {
157-
*G_DMA_BUFFER_ADDR.borrow(cs).borrow_mut() = Some(adc_buffer1_addr)
158-
});
159+
cortex_m::interrupt::free(|cs| *G_DMA_BUFFER_ADDR.borrow(cs).borrow_mut() = Some(adc_buffer1_addr));
160+
161+
159162

160163
//==================================================
161164
// Set up adc
@@ -174,25 +177,26 @@ fn main() -> ! {
174177
adc.prepare_injected(&mut pa3, InjTrigSource::TRG_2);
175178
adc.start_injected();
176179

180+
177181
// Enable timer to trigger external sources in mms value of cr2
178182
// 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
179183
// set (even if it was already high), as soon as a capture or a compare match occurred.
180184
// ouput is (TRGO)
181185
// according to reference manual chapter 22.4.2
182186
// this is only available on timer TIM2, TIM3, TIM4 and TIM1
183-
unsafe {
187+
unsafe{
184188
// get pointer of timer 2
185189
let tim = &(*stm32g0::stm32g031::TIM2::ptr());
186-
//
187-
tim.cr2.modify(|_, w| w.mms().bits(3 as u8));
190+
//
191+
tim.cr2.modify(|_,w| w.mms().bits(3 as u8));
188192
}
189193

190194
// enable dma to be called, when adc is ready to read
191195
adc.dma_enable(true);
192196
adc.dma_circualr_mode(true);
193197

194198
// don't enabel the timer bevor the dma
195-
// Set up a timer expiring after
199+
// Set up a timer expiring after
196200
timer.start(50.us());
197201
timer.listen();
198202

@@ -201,5 +205,7 @@ fn main() -> ! {
201205
cortex_m::peripheral::NVIC::unmask(Interrupt::DMA_CHANNEL1);
202206
}
203207

204-
loop {}
208+
loop {
209+
210+
}
205211
}

‎src/analog/adc.rs

Lines changed: 41 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -75,16 +75,17 @@ pub enum AsyncClockDiv {
7575
/// ADC injected trigger source selection
7676
#[derive(Copy, Clone, PartialEq)]
7777
pub enum InjTrigSource {
78-
TRG_0 = 0b000, // TIM1_TRGO2
79-
TRG_1 = 0b001, // TIM1_CC4
80-
TRG_2 = 0b010, // TIM2_TRGO
81-
TRG_3 = 0b011, // TIM3_TRGO
82-
TRG_4 = 0b100, // TIM15_TRGO
83-
TRG_5 = 0b101, // TIM6_TRGO
84-
TRG_6 = 0b110, // TIM4_TRGO
85-
TRG_7 = 0b111, // EXTI11
78+
TRG_0 = 0b000, // TIM1_TRGO2
79+
TRG_1 = 0b001, // TIM1_CC4
80+
TRG_2 = 0b010, // TIM2_TRGO
81+
TRG_3 = 0b011, // TIM3_TRGO
82+
TRG_4 = 0b100, // TIM15_TRGO
83+
TRG_5 = 0b101, // TIM6_TRGO
84+
TRG_6 = 0b110, // TIM4_TRGO
85+
TRG_7 = 0b111, // EXTI11
8686
}
8787

88+
8889
/// Analog to Digital converter interface
8990
pub struct Adc {
9091
rb: ADC,
@@ -193,10 +194,8 @@ impl Adc {
193194
}
194195

195196
/// The nuber of bits, the oversampling result is shifted in bits at the end of oversampling
196-
pub fn set_oversamling_shift(&mut self, nrbits: u8) {
197-
self.rb
198-
.cfgr2
199-
.modify(|_, w| unsafe { w.ovss().bits(nrbits) });
197+
pub fn set_oversamling_shift(&mut self, nrbits:u8) {
198+
self.rb.cfgr2.modify(|_, w| unsafe {w.ovss().bits(nrbits)});
200199
}
201200

202201
/// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
@@ -209,27 +208,25 @@ impl Adc {
209208
/// 110: 128x
210209
/// 111: 256x
211210
212-
pub fn set_oversamling_ratio(&mut self, multyply: u8) {
213-
self.rb
214-
.cfgr2
215-
.modify(|_, w| unsafe { w.ovsr().bits(multyply) });
211+
pub fn set_oversamling_ratio(&mut self, multyply:u8) {
212+
self.rb.cfgr2.modify(|_, w| unsafe {w.ovsr().bits(multyply)});
216213
}
217214

218215
pub fn oversamling_enable(&mut self) {
219-
self.rb.cfgr2.modify(|_, w| unsafe { w.ovse().set_bit() });
216+
self.rb.cfgr2.modify(|_, w| unsafe {w.ovse().set_bit()});
220217
}
221218

222219
pub fn start_injected(&mut self) {
223-
self.rb.cr.modify(|_, w| w.adstart().set_bit());
220+
self.rb.cr.modify(|_,w| w.adstart().set_bit());
224221
// ADSTART bit is cleared to 0 bevor using this function
225222
// enable self.rb.isr.eos() flag is set after each converstion
226223
self.rb.ier.modify(|_, w| w.eocie().set_bit()); // end of sequence interupt enable
227224
}
228225

229-
pub fn stop_injected(&mut self) {
230-
// ?????? or is it reset after each conversion?
226+
227+
pub fn stop_injected(&mut self) { // ?????? or is it reset after each conversion?
231228
// ADSTART bit is cleared to 0 bevor using this function
232-
// disable EOS interrupt
229+
// disable EOS interrupt
233230
// maybe self.rb.cr.adstp().set_bit() must be performed before interrupt is disabled + wait abortion
234231
self.rb.ier.modify(|_, w| w.eocie().clear_bit()); // end of sequence interupt disable
235232
}
@@ -258,32 +255,39 @@ where
258255
{
259256
type Error = ();
260257

261-
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
262-
// set the clock mode to synchronous one
258+
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource){
259+
// set the clock mode to synchronous one
263260
// self.rb.cfgr2.ckmode().bits(CLCOKMODE) // CLOCKMODE = 01 or 10 for PCLK/2 or PCLK/4
264261

262+
265263
// self.set_injected_trigger_source(triger_source as InjTrigSource);
266-
self.rb
267-
.cfgr1
268-
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });
264+
self.rb.cfgr1.modify(|_, w| unsafe {
265+
w.exten()
266+
.bits(1)
267+
.extsel()
268+
.bits(triger_source as u8)
269+
});
269270

270271
self.rb.cfgr1.modify(|_, w| unsafe {
271-
w.res() // set ADC resolution bits (ADEN must be =0)
272+
w.res() // set ADC resolution bits (ADEN must be =0)
272273
.bits(self.precision as u8)
273-
.align() // set alignment bit is (ADSTART must be 0)
274+
.align() // set alignment bit is (ADSTART must be 0)
274275
.bit(self.align == Align::Left)
275276
});
276277

277278
self.power_up();
278279

279280
self.rb
280-
.smpr // set sampling time set 1 (ADSTART must be 0)
281+
.smpr // set sampling time set 1 (ADSTART must be 0)
281282
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
282283

283284
self.rb
284-
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
285+
.chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
285286
.modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
287+
286288
}
289+
290+
287291
}
288292

289293
pub trait DmaMode<ADC> {
@@ -294,25 +298,27 @@ pub trait DmaMode<ADC> {
294298
}
295299

296300
impl DmaMode<Adc> for Adc {
301+
297302
type Error = ();
298303

299304
fn dma_enable(&mut self, enable: bool) {
300305
if enable {
301-
self.rb.cfgr1.modify(|_, w| w.dmaen().set_bit()); // enable dma beeing called
306+
self.rb.cfgr1.modify(|_,w| w.dmaen().set_bit()); // enable dma beeing called
302307
} else {
303-
self.rb.cfgr1.modify(|_, w| w.dmaen().clear_bit()); // disable dma beeing called
308+
self.rb.cfgr1.modify(|_,w| w.dmaen().clear_bit()); // disable dma beeing called
304309
}
305310
}
306-
311+
307312
fn dma_circualr_mode(&mut self, enable: bool) {
308313
if enable {
309-
self.rb.cfgr1.modify(|_, w| w.dmacfg().set_bit()); // activate circular mode
314+
self.rb.cfgr1.modify(|_,w| w.dmacfg().set_bit()); // activate circular mode
310315
} else {
311-
self.rb.cfgr1.modify(|_, w| w.dmacfg().clear_bit()); // disable circular mode
316+
self.rb.cfgr1.modify(|_,w| w.dmacfg().clear_bit()); // disable circular mode
312317
}
313318
}
314319
}
315320

321+
316322
impl<WORD, PIN> OneShot<Adc, WORD, PIN> for Adc
317323
where
318324
WORD: From<u16>,

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