demacrofy DMA

Author: burrbull

src/dma.rs

@@ -1,9 +1,9 @@
 //! Direct Memory Access Engine
 
 // TODO: add DMA2 for B1, C1
-use crate::dmamux::DmaMuxIndex;
-use crate::rcc::Rcc;
-use crate::stm32::DMAMUX;
+use crate::dmamux::{self, DmaMuxExt, DmaMuxIndex};
+use crate::rcc::{Enable, Rcc, Reset};
+use crate::stm32::{self, DMA1 as DMA, DMAMUX};
 
 /// Extension trait to split a DMA peripheral into independent channels
 pub trait DmaExt {
@@ -243,6 +243,57 @@ pub trait Channel: private::Channel {
     }
 }
 
+/// Singleton that represents a DMA channel
+pub struct C<const N: u8> {
+    mux: dmamux::Channel<N>,
+}
+
+impl<const N: u8> private::Channel for C<N> {
+    fn ch(&self) -> &stm32::dma1::CH {
+        // NOTE(unsafe) $Ci grants exclusive access to this register
+        unsafe { &(*DMA::ptr()).ch(N as usize) }
+    }
+}
+
+impl<const N: u8> C<N> {
+    pub fn mux(&mut self) -> &mut dyn dmamux::DmaMuxChannel {
+        &mut self.mux
+    }
+}
+
+impl<const N: u8> Channel for C<N> {
+    fn select_peripheral(&mut self, index: DmaMuxIndex) {
+        self.mux().select_peripheral(index);
+    }
+
+    fn event_occurred(&self, event: Event) -> bool {
+        use Event::*;
+
+        // NOTE(unsafe) atomic read
+        let flags = unsafe { (*DMA::ptr()).isr().read() };
+        match event {
+            HalfTransfer => flags.htif(N).bit_is_set(),
+            TransferComplete => flags.tcif(N).bit_is_set(),
+            TransferError => flags.teif(N).bit_is_set(),
+            Any => flags.gif(N).bit_is_set(),
+        }
+    }
+
+    fn clear_event(&mut self, event: Event) {
+        use Event::*;
+
+        // NOTE(unsafe) atomic write to a stateless register
+        unsafe {
+            let _ = &(*DMA::ptr()).ifcr().write(|w| match event {
+                HalfTransfer => w.chtif(N).set_bit(),
+                TransferComplete => w.ctcif(N).set_bit(),
+                TransferError => w.cteif(N).set_bit(),
+                Any => w.cgif(N).set_bit(),
+            });
+        }
+    }
+}
+
 macro_rules! dma {
     (
         channels: {
@@ -251,11 +302,6 @@ macro_rules! dma {
             )+
         },
     ) => {
-        use crate::dmamux;
-        use crate::rcc::{Enable, Reset};
-        use crate::stm32::{self, DMA1 as DMA};
-        use crate::dmamux::DmaMuxExt;
-
         /// DMA channels
         pub struct Channels {
             $( pub $chi: $Ci, )+
@@ -269,60 +315,8 @@ macro_rules! dma {
             }
         }
 
-
         $(
-            /// Singleton that represents a DMA channel
-            pub struct $Ci {
-                mux: dmamux::Channel<$i>,
-            }
-
-            impl private::Channel for $Ci {
-                fn ch(&self) -> &stm32::dma1::CH {
-                    // NOTE(unsafe) $Ci grants exclusive access to this register
-                    unsafe { &(*DMA::ptr()).ch($i) }
-                }
-            }
-
-            impl $Ci {
-                pub fn mux(&mut self) -> &mut dyn dmamux::DmaMuxChannel {
-                    &mut self.mux
-                }
-            }
-
-            impl Channel for $Ci {
-
-                fn select_peripheral(&mut self, index: DmaMuxIndex) {
-                    self.mux().select_peripheral(index);
-                }
-
-                fn event_occurred(&self, event: Event) -> bool {
-                    use Event::*;
-
-                    // NOTE(unsafe) atomic read
-                    let flags = unsafe { (*DMA::ptr()).isr().read() };
-                    match event {
-                        HalfTransfer => flags.htif($i).bit_is_set(),
-                        TransferComplete => flags.tcif($i).bit_is_set(),
-                        TransferError => flags.teif($i).bit_is_set(),
-                        Any => flags.gif($i).bit_is_set(),
-                    }
-                }
-
-                fn clear_event(&mut self, event: Event) {
-                    use Event::*;
-
-                    // NOTE(unsafe) atomic write to a stateless register
-                    unsafe {
-                        let _ = &(*DMA::ptr()).ifcr().write(|w| match event {
-                            HalfTransfer => w.chtif($i).set_bit(),
-                            TransferComplete => w.ctcif($i).set_bit(),
-                            TransferError => w.cteif($i).set_bit(),
-                            Any => w.cgif($i).set_bit(),
-                        });
-                    }
-                }
-
-            }
+            pub type $Ci = C<$i>;
         )+
     }
 }

src/dmamux.rs

@@ -149,13 +149,12 @@ pub trait DmaMuxChannel {
     fn select_peripheral(&mut self, index: DmaMuxIndex);
 }
 
-pub struct Channel<const N: usize> {
-    _0: (),
-}
+#[non_exhaustive]
+pub struct Channel<const N: u8>;
 
-impl<const N: usize> DmaMuxChannel for Channel<N> {
+impl<const N: u8> DmaMuxChannel for Channel<N> {
     fn select_peripheral(&mut self, index: DmaMuxIndex) {
-        let reg = unsafe { &(*DMAMUX::ptr()).ccr(N) };
+        let reg = unsafe { &(*DMAMUX::ptr()).ccr(N as usize) };
         reg.write(|w| unsafe { w.dmareq_id().bits(index.val()).ege().set_bit() });
     }
 }
@@ -193,27 +192,27 @@ impl DmaMuxExt for DMAMUX {
 
     fn split(self) -> Self::Channels {
         Channels {
-            ch0: Channel::<0> { _0: () },
-            ch1: Channel::<1> { _0: () },
-            ch2: Channel::<2> { _0: () },
-            ch3: Channel::<3> { _0: () },
-            ch4: Channel::<4> { _0: () },
+            ch0: Channel::<0>,
+            ch1: Channel::<1>,
+            ch2: Channel::<2>,
+            ch3: Channel::<3>,
+            ch4: Channel::<4>,
             #[cfg(any(
                 feature = "stm32g070",
                 feature = "stm32g071",
                 feature = "stm32g081",
                 feature = "stm32g0b1",
                 feature = "stm32g0c1",
             ))]
-            ch5: Channel::<5> { _0: () },
+            ch5: Channel::<5>,
             #[cfg(any(
                 feature = "stm32g070",
                 feature = "stm32g071",
                 feature = "stm32g081",
                 feature = "stm32g0b1",
                 feature = "stm32g0c1",
             ))]
-            ch6: Channel::<6> { _0: () },
+            ch6: Channel::<6>,
         }
     }
 }