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rcc refactoring
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13 files changed

+155
-87
lines changed

13 files changed

+155
-87
lines changed

‎src/analog/adc.rs‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -304,10 +304,6 @@ where
304304
type Error = ();
305305

306306
fn prepare_injected(&mut self, _pin: &mut PIN, triger_source: InjTrigSource) {
307-
// set the clock mode to synchronous one
308-
// self.rb.cfgr2.ckmode().bits(CLCOKMODE) // CLOCKMODE = 01 or 10 for PCLK/2 or PCLK/4
309-
310-
// self.set_injected_trigger_source(triger_source as InjTrigSource);
311307
self.rb
312308
.cfgr1
313309
.modify(|_, w| unsafe { w.exten().bits(1).extsel().bits(triger_source as u8) });

‎src/analog/dac.rs‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use core::mem::MaybeUninit;
55

66
use crate::gpio::gpioa::{PA4, PA5};
77
use crate::gpio::DefaultMode;
8-
use crate::rcc::Rcc;
8+
use crate::rcc::*;
99
use crate::stm32::DAC;
1010
use hal::blocking::delay::DelayUs;
1111

@@ -74,16 +74,29 @@ impl Pins<DAC> for (PA4<DefaultMode>, PA5<DefaultMode>) {
7474
type Output = (Channel1<Disabled>, Channel2<Disabled>);
7575
}
7676

77+
impl Enable for DAC {
78+
fn enable(rcc: &mut Rcc) {
79+
rcc.rb.apbenr1.modify(|_, w| w.dac1en().set_bit());
80+
}
81+
82+
fn disable(rcc: &mut Rcc) {
83+
rcc.rb.apbenr1.modify(|_, w| w.dac1en().clear_bit());
84+
}
85+
}
86+
87+
impl Reset for DAC {
88+
fn reset(rcc: &mut Rcc) {
89+
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().set_bit());
90+
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().clear_bit());
91+
}
92+
}
93+
7794
pub fn dac<PINS>(_dac: DAC, _pins: PINS, rcc: &mut Rcc) -> PINS::Output
7895
where
7996
PINS: Pins<DAC>,
8097
{
81-
// Enable DAC clocks
82-
rcc.rb.apbenr1.modify(|_, w| w.dac1en().set_bit());
83-
84-
// Reset DAC
85-
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().set_bit());
86-
rcc.rb.apbrstr1.modify(|_, w| w.dac1rst().clear_bit());
98+
DAC::enable(rcc);
99+
DAC::reset(rcc);
87100

88101
#[allow(clippy::uninit_assumed_init)]
89102
unsafe {

‎src/i2c.rs‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use hal::blocking::i2c::{Read, Write, WriteRead};
33

44
use crate::gpio::{gpioa::*, gpiob::*};
55
use crate::gpio::{AltFunction, OpenDrain, Output};
6-
use crate::rcc::Rcc;
6+
use crate::rcc::*;
77
use crate::stm32::{I2C1, I2C2};
88
use crate::time::Hertz;
99
use core::cmp;
@@ -176,6 +176,23 @@ macro_rules! i2c {
176176
}
177177
)+
178178

179+
impl Enable for $I2CX {
180+
fn enable(rcc: &mut Rcc){
181+
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().set_bit());
182+
}
183+
184+
fn disable(rcc: &mut Rcc) {
185+
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().clear_bit());
186+
}
187+
}
188+
189+
impl Reset for $I2CX {
190+
fn reset(rcc: &mut Rcc){
191+
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().set_bit());
192+
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().clear_bit());
193+
}
194+
}
195+
179196
impl I2cExt<$I2CX> for $I2CX {
180197
fn i2c<SDA, SCL>(
181198
self,
@@ -201,12 +218,8 @@ macro_rules! i2c {
201218
SDA: SDAPin<$I2CX>,
202219
SCL: SCLPin<$I2CX>,
203220
{
204-
// Enable clock for I2C
205-
rcc.rb.apbenr1.modify(|_, w| w.$i2cxen().set_bit());
206-
207-
// Reset I2C
208-
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().set_bit());
209-
rcc.rb.apbrstr1.modify(|_, w| w.$i2crst().clear_bit());
221+
$I2CX::enable(rcc);
222+
$I2CX::reset(rcc);
210223

211224
// Make sure the I2C unit is disabled so we can configure it
212225
i2c.cr1.modify(|_, w| w.pe().clear_bit());

‎src/lib.rs‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@ pub use crate::stm32::interrupt;
4646

4747
pub mod analog;
4848
pub mod crc;
49-
pub mod delay;
5049
pub mod dma;
5150
pub mod dmamux;
5251
pub mod exti;

‎src/prelude.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ pub use crate::analog::dac::DacExt as _;
1616
#[cfg(any(feature = "stm32g071", feature = "stm32g081"))]
1717
pub use crate::analog::dac::DacOut as _;
1818
pub use crate::crc::CrcExt as _;
19-
pub use crate::delay::DelayExt as _;
19+
pub use crate::timer::delay::DelayExt as _;
2020
// pub use crate::dma::CopyDma as _;
2121
pub use crate::dma::DmaExt as _;
2222
// pub use crate::dma::ReadDma as _;

‎src/rcc/mod.rs‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,3 +347,14 @@ impl RccExt for RCC {
347347
self.constrain().freeze(rcc_cfg)
348348
}
349349
}
350+
351+
/// Enable/disable peripheral
352+
pub trait Enable {
353+
fn enable(rcc: &mut Rcc);
354+
fn disable(rcc: &mut Rcc);
355+
}
356+
357+
/// Reset peripheral
358+
pub trait Reset {
359+
fn reset(rcc: &mut Rcc);
360+
}

‎src/serial/usart.rs‎

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use crate::dmamux::DmaMuxIndex;
66
use crate::gpio::AltFunction;
77
use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*};
88
use crate::prelude::*;
9-
use crate::rcc::Rcc;
9+
use crate::rcc::*;
1010
use crate::stm32::*;
1111

1212
use cortex_m::interrupt;
@@ -332,6 +332,16 @@ macro_rules! uart_basic {
332332
($USARTX:ident,
333333
$usartX:ident, $apbXenr:ident, $usartXen:ident, $clk_mul:expr
334334
) => {
335+
impl Enable for $USARTX {
336+
fn enable(rcc: &mut Rcc) {
337+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
338+
}
339+
340+
fn disable(rcc: &mut Rcc) {
341+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().clear_bit());
342+
}
343+
}
344+
335345
impl SerialExt<$USARTX, BasicConfig> for $USARTX {
336346
fn usart<TX, RX>(
337347
self,
@@ -361,7 +371,8 @@ macro_rules! uart_basic {
361371
RX: RxPin<$USARTX>,
362372
{
363373
// Enable clock for USART
364-
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
374+
$USARTX::enable(rcc);
375+
365376
let clk = rcc.clocks.apb_clk.0 as u64;
366377
let bdr = config.baudrate.0 as u64;
367378
let div = ($clk_mul * clk) / bdr;
@@ -462,6 +473,16 @@ macro_rules! uart_full {
462473
($USARTX:ident,
463474
$usartX:ident, $apbXenr:ident, $usartXen:ident, $clk_mul:expr
464475
) => {
476+
impl Enable for $USARTX {
477+
fn enable(rcc: &mut Rcc) {
478+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
479+
}
480+
481+
fn disable(rcc: &mut Rcc) {
482+
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().clear_bit());
483+
}
484+
}
485+
465486
impl SerialExt<$USARTX, FullConfig> for $USARTX {
466487
fn usart<TX, RX>(
467488
self,
@@ -491,7 +512,7 @@ macro_rules! uart_full {
491512
RX: RxPin<$USARTX>,
492513
{
493514
// Enable clock for USART
494-
rcc.rb.$apbXenr.modify(|_, w| w.$usartXen().set_bit());
515+
$USARTX::enable(rcc);
495516

496517
let clk = rcc.clocks.apb_clk.0 as u64;
497518
let bdr = config.baudrate.0 as u64;

‎src/delay.rs‎ renamed to ‎src/timer/delay.rs‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ use cortex_m::peripheral::SYST;
44
use hal::blocking::delay::{DelayMs, DelayUs};
55

66
use crate::prelude::*;
7-
use crate::rcc::Rcc;
7+
use crate::rcc::*;
88
use crate::stm32::*;
99
use crate::time::{Hertz, MicroSecond};
1010

@@ -92,14 +92,14 @@ impl DelayExt<SYST> for SYST {
9292
}
9393

9494
macro_rules! delays {
95-
($($TIM:ident: ($tim:ident, $timXen:ident, $timXrst:ident, $apbenr:ident, $apbrstr:ident),)+) => {
95+
($($TIM:ident: ($tim:ident, $timXen:ident, $timXrst:ident),)+) => {
9696
$(
9797
impl Delay<$TIM> {
9898
/// Configures $TIM timer as a delay provider
9999
pub fn $tim(tim: $TIM, rcc: &mut Rcc) -> Self {
100-
rcc.rb.$apbenr.modify(|_, w| w.$timXen().set_bit());
101-
rcc.rb.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
102-
rcc.rb.$apbrstr.modify(|_, w| w.$timXrst().clear_bit());
100+
$TIM::enable(rcc);
101+
$TIM::reset(rcc);
102+
103103
Delay {
104104
tim,
105105
clk: rcc.clocks.apb_tim_clk,
@@ -174,21 +174,21 @@ macro_rules! delays {
174174
}
175175

176176
delays! {
177-
TIM1: (tim1, tim1en, tim1rst, apbenr2, apbrstr2),
178-
TIM3: (tim3, tim3en, tim3rst, apbenr1, apbrstr1),
179-
TIM14: (tim14, tim14en, tim14rst, apbenr2, apbrstr2),
180-
TIM16: (tim16, tim16en, tim16rst, apbenr2, apbrstr2),
181-
TIM17: (tim17, tim17en, tim17rst, apbenr2, apbrstr2),
177+
TIM1: (tim1, tim1en, tim1rst),
178+
TIM3: (tim3, tim3en, tim3rst),
179+
TIM14: (tim14, tim14en, tim14rst),
180+
TIM16: (tim16, tim16en, tim16rst),
181+
TIM17: (tim17, tim17en, tim17rst),
182182
}
183183

184184
#[cfg(feature = "stm32g0x1")]
185185
delays! {
186-
TIM2: (tim2, tim2en, tim2rst, apbenr1, apbrstr1),
186+
TIM2: (tim2, tim2en, tim2rst),
187187
}
188188

189189
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
190190
delays! {
191-
TIM6: (tim6, tim6en, tim6rst, apbenr1, apbrstr1),
192-
TIM7: (tim7, tim7en, tim7rst, apbenr1, apbrstr1),
193-
TIM15: (tim15, tim15en, tim15rst, apbenr2, apbrstr2),
191+
TIM6: (tim6, tim6en, tim6rst),
192+
TIM7: (tim7, tim7en, tim7rst),
193+
TIM15: (tim15, tim15en, tim15rst),
194194
}

‎src/timer/mod.rs‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
//! Timers
2-
use crate::rcc::Rcc;
2+
use crate::rcc::*;
33
use crate::stm32::*;
44
use crate::time::{Hertz, MicroSecond};
55
use cortex_m::peripheral::syst::SystClkSource;
66
use cortex_m::peripheral::SYST;
77
use hal::timer::{CountDown, Periodic};
88
use void::Void;
99

10+
pub mod delay;
1011
pub mod opm;
1112
pub mod pins;
1213
pub mod pwm;
@@ -88,12 +89,28 @@ impl Periodic for Timer<SYST> {}
8889
macro_rules! timers {
8990
($($TIM:ident: ($tim:ident, $timXen:ident, $timXrst:ident, $apbenr:ident, $apbrstr:ident, $cnt:ident $(,$cnt_h:ident)*),)+) => {
9091
$(
91-
impl Timer<$TIM> {
92-
/// Configures a TIM peripheral as a periodic count down timer
93-
pub fn $tim<T>(tim: $TIM, rcc: &mut Rcc) -> Self {
92+
impl Enable for $TIM {
93+
fn enable(rcc: &mut Rcc){
9494
rcc.rb.$apbenr.modify(|_, w| w.$timXen().set_bit());
95+
}
96+
97+
fn disable(rcc: &mut Rcc) {
98+
rcc.rb.$apbenr.modify(|_, w| w.$timXen().clear_bit());
99+
}
100+
}
101+
102+
impl Reset for $TIM {
103+
fn reset(rcc: &mut Rcc){
95104
rcc.rb.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
96105
rcc.rb.$apbrstr.modify(|_, w| w.$timXrst().clear_bit());
106+
}
107+
}
108+
109+
impl Timer<$TIM> {
110+
/// Configures a TIM peripheral as a periodic count down timer
111+
pub fn $tim<T>(tim: $TIM, rcc: &mut Rcc) -> Self {
112+
$TIM::enable(rcc);
113+
$TIM::reset(rcc);
97114

98115
Timer {
99116
tim,

‎src/timer/opm.rs‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//! # One-pulse Mode
22
use crate::prelude::*;
3-
use crate::rcc::Rcc;
3+
use crate::rcc::*;
44
use crate::stm32::*;
55
use crate::time::{Hertz, MicroSecond};
66
use crate::timer::pins::TimerPin;
@@ -39,7 +39,7 @@ impl<TIM> Opm<TIM> {
3939
}
4040

4141
macro_rules! opm {
42-
($($TIMX:ident: ($apbXenr:ident, $apbXrstr:ident, $timX:ident, $timXen:ident, $timXrst:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
42+
($($TIMX:ident: ($timX:ident, $timXen:ident, $timXrst:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
4343
$(
4444
impl OpmExt for $TIMX {
4545
fn opm(self, period: MicroSecond, rcc: &mut Rcc) -> Opm<Self> {
@@ -48,9 +48,8 @@ macro_rules! opm {
4848
}
4949

5050
fn $timX(tim: $TIMX, period: MicroSecond, rcc: &mut Rcc) -> Opm<$TIMX> {
51-
rcc.rb.$apbXenr.modify(|_, w| w.$timXen().set_bit());
52-
rcc.rb.$apbXrstr.modify(|_, w| w.$timXrst().set_bit());
53-
rcc.rb.$apbXrstr.modify(|_, w| w.$timXrst().clear_bit());
51+
$TIMX::enable(rcc);
52+
$TIMX::reset(rcc);
5453

5554
let cycles_per_period = rcc.clocks.apb_tim_clk / period.into();
5655
let psc = (cycles_per_period - 1) / 0xffff;
@@ -142,19 +141,19 @@ opm_hal! {
142141
}
143142

144143
opm! {
145-
TIM1: (apbenr2, apbrstr2, tim1, tim1en, tim1rst, arr),
146-
TIM3: (apbenr1, apbrstr1, tim3, tim3en, tim3rst, arr_l, arr_h),
147-
TIM14: (apbenr2, apbrstr2, tim14, tim14en, tim14rst, arr),
148-
TIM16: (apbenr2, apbrstr2, tim16, tim16en, tim16rst, arr),
149-
TIM17: (apbenr2, apbrstr2, tim17, tim17en, tim17rst, arr),
144+
TIM1: (tim1, tim1en, tim1rst, arr),
145+
TIM3: (tim3, tim3en, tim3rst, arr_l, arr_h),
146+
TIM14: (tim14, tim14en, tim14rst, arr),
147+
TIM16: (tim16, tim16en, tim16rst, arr),
148+
TIM17: (tim17, tim17en, tim17rst, arr),
150149
}
151150

152151
#[cfg(feature = "stm32g0x1")]
153152
opm! {
154-
TIM2: (apbenr1, apbrstr1, tim2, tim2en, tim2rst, arr_l, arr_h),
153+
TIM2: (tim2, tim2en, tim2rst, arr_l, arr_h),
155154
}
156155

157156
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
158157
opm! {
159-
TIM15: (apbenr2, apbrstr2, tim15, tim15en, tim15rst, arr),
158+
TIM15: (tim15, tim15en, tim15rst, arr),
160159
}

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