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rcc macros cleanup
1 parent 35ee1d9 commit 946d036

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8 files changed

+62
-47
lines changed

8 files changed

+62
-47
lines changed

‎src/dma.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -308,7 +308,7 @@ macro_rules! dma {
308308

309309
// NOTE(unsafe) atomic write to a stateless register
310310
unsafe {
311-
&(*DMA::ptr()).ifcr.write(|w| match event {
311+
let _ = &(*DMA::ptr()).ifcr.write(|w| match event {
312312
HalfTransfer => w.$chtifi().set_bit(),
313313
TransferComplete => w.$ctcifi().set_bit(),
314314
TransferError => w.$cteifi().set_bit(),

‎src/gpio.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -313,7 +313,7 @@ macro_rules! gpio {
313313
pub fn listen(self, edge: SignalEdge, exti: &mut EXTI) -> $PXi<Input<Floating>> {
314314
let offset = 2 * $i;
315315
unsafe {
316-
&(*$GPIOX::ptr()).pupdr.modify(|r, w| {
316+
let _ = &(*$GPIOX::ptr()).pupdr.modify(|r, w| {
317317
w.bits(r.bits() & !(0b11 << offset))
318318
});
319319
&(*$GPIOX::ptr()).moder.modify(|r, w| {

‎src/spi.rs

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiod::*, AltFunction, DefaultMode};
2-
use crate::rcc::Rcc;
2+
use crate::rcc::*;
33
use crate::stm32::{SPI1, SPI2};
44
use crate::time::Hertz;
55
use core::ptr;
@@ -137,6 +137,23 @@ macro_rules! spi {
137137
}
138138
)*
139139

140+
impl Enable for $SPIX {
141+
fn enable(rcc: &mut Rcc){
142+
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().set_bit());
143+
}
144+
145+
fn disable(rcc: &mut Rcc) {
146+
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().clear_bit());
147+
}
148+
}
149+
150+
impl Reset for $SPIX {
151+
fn reset(rcc: &mut Rcc){
152+
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().set_bit());
153+
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().clear_bit());
154+
}
155+
}
156+
140157
impl<PINS: Pins<$SPIX>> Spi<$SPIX, PINS> {
141158
pub fn $spiX<T>(
142159
spi: $SPIX,
@@ -148,10 +165,8 @@ macro_rules! spi {
148165
where
149166
T: Into<Hertz>
150167
{
151-
// Enable clock for SPI
152-
rcc.rb.$apbXenr.modify(|_, w| w.$spiXen().set_bit());
153-
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().set_bit());
154-
rcc.rb.$apbXrst.modify(|_, w| w.$spiXrst().clear_bit());
168+
$SPIX::enable(rcc);
169+
$SPIX::reset(rcc);
155170

156171
// disable SS output
157172
spi.cr2.write(|w| w.ssoe().clear_bit());

‎src/timer/delay.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@ impl DelayExt<SYST> for SYST {
9292
}
9393

9494
macro_rules! delays {
95-
($($TIM:ident: ($tim:ident, $timXen:ident, $timXrst:ident),)+) => {
95+
($($TIM:ident: $tim:ident,)+) => {
9696
$(
9797
impl Delay<$TIM> {
9898
/// Configures $TIM timer as a delay provider
@@ -174,21 +174,21 @@ macro_rules! delays {
174174
}
175175

176176
delays! {
177-
TIM1: (tim1, tim1en, tim1rst),
178-
TIM3: (tim3, tim3en, tim3rst),
179-
TIM14: (tim14, tim14en, tim14rst),
180-
TIM16: (tim16, tim16en, tim16rst),
181-
TIM17: (tim17, tim17en, tim17rst),
177+
TIM1: tim1,
178+
TIM3: tim3,
179+
TIM14: tim14,
180+
TIM16: tim16,
181+
TIM17: tim17,
182182
}
183183

184184
#[cfg(feature = "stm32g0x1")]
185185
delays! {
186-
TIM2: (tim2, tim2en, tim2rst),
186+
TIM2: tim2,
187187
}
188188

189189
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
190190
delays! {
191-
TIM6: (tim6, tim6en, tim6rst),
192-
TIM7: (tim7, tim7en, tim7rst),
193-
TIM15: (tim15, tim15en, tim15rst),
191+
TIM6: tim6,
192+
TIM7: tim7,
193+
TIM15: tim15,
194194
}

‎src/timer/opm.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ impl<TIM> Opm<TIM> {
3939
}
4040

4141
macro_rules! opm {
42-
($($TIMX:ident: ($timX:ident, $timXen:ident, $timXrst:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
42+
($($TIMX:ident: ($timX:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
4343
$(
4444
impl OpmExt for $TIMX {
4545
fn opm(self, period: MicroSecond, rcc: &mut Rcc) -> Opm<Self> {
@@ -141,19 +141,19 @@ opm_hal! {
141141
}
142142

143143
opm! {
144-
TIM1: (tim1, tim1en, tim1rst, arr),
145-
TIM3: (tim3, tim3en, tim3rst, arr_l, arr_h),
146-
TIM14: (tim14, tim14en, tim14rst, arr),
147-
TIM16: (tim16, tim16en, tim16rst, arr),
148-
TIM17: (tim17, tim17en, tim17rst, arr),
144+
TIM1: (tim1, arr),
145+
TIM3: (tim3, arr_l, arr_h),
146+
TIM14: (tim14, arr),
147+
TIM16: (tim16, arr),
148+
TIM17: (tim17, arr),
149149
}
150150

151151
#[cfg(feature = "stm32g0x1")]
152152
opm! {
153-
TIM2: (tim2, tim2en, tim2rst, arr_l, arr_h),
153+
TIM2: (tim2, arr_l, arr_h),
154154
}
155155

156156
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
157157
opm! {
158-
TIM15: (tim15, tim15en, tim15rst, arr),
158+
TIM15: (tim15, arr),
159159
}

‎src/timer/pwm.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ impl<TIM> Pwm<TIM> {
3636
}
3737

3838
macro_rules! pwm {
39-
($($TIMX:ident: ($timX:ident, $timXen:ident, $timXrst:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
39+
($($TIMX:ident: ($timX:ident, $arr:ident $(,$arr_h:ident)*),)+) => {
4040
$(
4141
impl PwmExt for $TIMX {
4242
fn pwm<T>(self, freq: T, rcc: &mut Rcc) -> Pwm<Self>
@@ -189,19 +189,19 @@ pwm_hal! {
189189
}
190190

191191
pwm! {
192-
TIM1: (tim1, tim1en, tim1rst, arr),
193-
TIM3: (tim3, tim3en, tim3rst, arr_l, arr_h),
194-
TIM14: (tim14, tim14en, tim14rst, arr),
195-
TIM16: (tim16, tim16en, tim16rst, arr),
196-
TIM17: (tim17, tim17en, tim17rst, arr),
192+
TIM1: (tim1, arr),
193+
TIM3: (tim3, arr_l, arr_h),
194+
TIM14: (tim14, arr),
195+
TIM16: (tim16, arr),
196+
TIM17: (tim17, arr),
197197
}
198198

199199
#[cfg(feature = "stm32g0x1")]
200200
pwm! {
201-
TIM2: (tim2, tim2en, tim2rst, arr_l, arr_h),
201+
TIM2: (tim2, arr_l, arr_h),
202202
}
203203

204204
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
205205
pwm! {
206-
TIM15: (tim15, tim15en, tim15rst, arr),
206+
TIM15: (tim15, arr),
207207
}

‎src/timer/qei.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ where
4343
}
4444

4545
macro_rules! qei {
46-
($($TIMX:ident: ($tim:ident, $timXen:ident, $timXrst:ident, $arr:ident, $cnt:ident),)+) => {
46+
($($TIMX:ident: ($tim:ident, $arr:ident, $cnt:ident),)+) => {
4747
$(
4848
impl<PINS> Qei<$TIMX, PINS> where PINS: QeiPins<$TIMX> {
4949
fn $tim(tim: $TIMX, pins: PINS, rcc: &mut Rcc) -> Self {
@@ -112,11 +112,11 @@ macro_rules! qei {
112112
}
113113

114114
qei! {
115-
TIM1: (tim1, tim1en, tim1rst, arr, cnt),
116-
TIM3: (tim3, tim3en, tim3rst, arr_l, cnt_l),
115+
TIM1: (tim1, arr, cnt),
116+
TIM3: (tim3, arr_l, cnt_l),
117117
}
118118

119119
#[cfg(feature = "stm32g0x1")]
120120
qei! {
121-
TIM2: (tim2, tim2en, tim2rst, arr_l, cnt_l),
121+
TIM2: (tim2, arr_l, cnt_l),
122122
}

‎src/timer/stopwatch.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ pub struct Stopwatch<TIM> {
1212
}
1313

1414
macro_rules! stopwatches {
15-
($($TIM:ident: ($tim:ident),)+) => {
15+
($($TIM:ident: $tim:ident,)+) => {
1616
$(
1717
impl Stopwatch<$TIM> {
1818
pub fn $tim(tim: $TIM, rcc: &mut Rcc) -> Self {
@@ -95,21 +95,21 @@ macro_rules! stopwatches {
9595
}
9696

9797
stopwatches! {
98-
TIM1: (tim1, tim1en, tim1rst),
99-
TIM3: (tim3, tim3en, tim3rst),
100-
TIM14: (tim14, tim14en, tim14rst),
101-
TIM16: (tim16, tim16en, tim16rst),
102-
TIM17: (tim17, tim17en, tim17rst),
98+
TIM1: tim1,
99+
TIM3: tim3,
100+
TIM14: tim14,
101+
TIM16: tim16,
102+
TIM17: tim17,
103103
}
104104

105105
#[cfg(feature = "stm32g0x1")]
106106
stopwatches! {
107-
TIM2: (tim2, tim2en, tim2rst),
107+
TIM2: tim2,
108108
}
109109

110110
#[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
111111
stopwatches! {
112-
TIM6: (tim6, tim6en, tim6rst),
113-
TIM7: (tim7, tim7en, tim7rst),
114-
TIM15: (tim15, tim15en, tim15rst),
112+
TIM6: tim6,
113+
TIM7: tim7,
114+
TIM15: tim15,
115115
}

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