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burrbullburrbull
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safe set
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7 files changed

+106
-126
lines changed

7 files changed

+106
-126
lines changed

‎src/analog/adc.rs‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -133,12 +133,10 @@ impl Adc {
133133
pub fn set_clock_source(&mut self, clock_source: ClockSource) {
134134
match clock_source {
135135
ClockSource::Pclk(div) => {
136-
self.rb
137-
.cfgr2()
138-
.modify(|_, w| unsafe { w.ckmode().bits(div as u8) });
136+
self.rb.cfgr2().modify(|_, w| w.ckmode().set(div as u8));
139137
}
140138
ClockSource::Async(div) => {
141-
self.rb.cfgr2().modify(|_, w| unsafe { w.ckmode().bits(0) });
139+
self.rb.cfgr2().modify(|_, w| w.ckmode().set(0));
142140
self.rb
143141
.ccr()
144142
.modify(|_, w| unsafe { w.presc().bits(div as u8) });
@@ -176,9 +174,7 @@ impl Adc {
176174
///
177175
/// Do not call if an ADC reading is ongoing.
178176
pub fn set_calibration(&mut self, calfact: CalibrationFactor) {
179-
self.rb
180-
.calfact()
181-
.write(|w| unsafe { w.calfact().bits(calfact.0) });
177+
self.rb.calfact().write(|w| w.calfact().set(calfact.0));
182178
}
183179

184180
/// Set the Adc sampling time
@@ -205,9 +201,7 @@ impl Adc {
205201

206202
/// Oversampling of adc according to datasheet of stm32g0, when oversampling is enabled
207203
pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
208-
self.rb
209-
.cfgr2()
210-
.modify(|_, w| unsafe { w.ovsr().bits(ratio as u8) });
204+
self.rb.cfgr2().modify(|_, w| w.ovsr().set(ratio as u8));
211205
}
212206

213207
pub fn oversampling_enable(&mut self, enable: bool) {
@@ -360,7 +354,7 @@ where
360354

361355
self.rb
362356
.smpr() // set sampling time set 1 (ADSTART must be 0)
363-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
357+
.modify(|_, w| w.smp1().set(self.sample_time as u8));
364358

365359
self.rb
366360
.chselr0() // set active channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
@@ -413,7 +407,7 @@ where
413407

414408
self.rb
415409
.smpr()
416-
.modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
410+
.modify(|_, w| w.smp1().set(self.sample_time as u8));
417411

418412
self.rb
419413
.chselr0()

‎src/i2c/blocking.rs‎

Lines changed: 76 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ macro_rules! flush_txdr {
3737
($i2c:expr) => {
3838
// If a pending TXIS flag is set, write dummy data to TXDR
3939
if $i2c.isr().read().txis().bit_is_set() {
40-
$i2c.txdr().write(|w| unsafe { w.txdata().bits(0) });
40+
$i2c.txdr().write(|w| w.txdata().set(0));
4141
}
4242

4343
// If TXDR is not flagged as empty, write 1 to flush it
@@ -78,8 +78,9 @@ macro_rules! busy_wait {
7878
} else if isr.tcr().bit_is_set() {
7979
// This condition Will only happen when reload == 1 and sbr == 1 (slave) and nbytes was written.
8080
// Send a NACK, set nbytes to clear tcr flag
81-
$i2c.cr2().modify(|_, w| unsafe {
82-
w.nack().set_bit().nbytes().bits(1 as u8)
81+
$i2c.cr2().modify(|_, w| {
82+
w.nack().set_bit();
83+
w.nbytes().set(1 as u8)
8384
});
8485
// Make one extra loop here to wait on the stop condition
8586
} else if isr.addr().bit_is_set() {
@@ -176,13 +177,10 @@ macro_rules! i2c {
176177
i2c.timingr().write(|w| unsafe { w.bits(timing_bits) });
177178

178179
// Enable the I2C processing
179-
i2c.cr1().modify(|_, w| unsafe {
180-
w.pe()
181-
.set_bit()
182-
.dnf()
183-
.bits(config.digital_filter)
184-
.anfoff()
185-
.bit(!config.analog_filter)
180+
i2c.cr1().modify(|_, w| {
181+
w.pe().set_bit();
182+
w.dnf().set(config.digital_filter);
183+
w.anfoff().bit(!config.analog_filter)
186184
});
187185

188186
if config.slave_address_1 > 0 {
@@ -196,10 +194,10 @@ macro_rules! i2c {
196194
}
197195

198196
if config.slave_address_2 > 0 {
199-
i2c.oar2().write( |w| unsafe {
200-
w.oa2msk().bits(config.slave_address_mask as u8)
201-
.oa2().bits(config.slave_address_2)
202-
.oa2en().set_bit()
197+
i2c.oar2().write(|w| {
198+
w.oa2msk().set(config.slave_address_mask as u8);
199+
w.oa2().set(config.slave_address_2);
200+
w.oa2en().set_bit()
203201
});
204202
// Enable acknowlidge control
205203
i2c.cr1().modify(|_, w| w.sbc().set_bit() );
@@ -265,21 +263,20 @@ macro_rules! i2c {
265263
// Set START and prepare to send `bytes`.
266264
// The START bit can be set even if the bus is BUSY or
267265
// I2C is in slave mode.
268-
self.i2c.cr2().write(|w| unsafe {
269-
w
270-
// Set number of bytes to transfer
271-
.nbytes().bits(sndlen as u8)
272-
// Set address to transfer to/from
273-
.sadd().bits((addr << 1) as u16)
274-
// 7-bit addressing mode
275-
.add10().clear_bit()
276-
// Set transfer direction to write
277-
.rd_wrn().clear_bit()
278-
// Software end mode
279-
.autoend().clear_bit()
280-
.reload().clear_bit()
281-
// Start transfer
282-
.start().set_bit()
266+
self.i2c.cr2().write(|w| {
267+
// Set number of bytes to transfer
268+
w.nbytes().set(sndlen as u8);
269+
// Set address to transfer to/from
270+
w.sadd().set((addr << 1) as u16);
271+
// 7-bit addressing mode
272+
w.add10().clear_bit();
273+
// Set transfer direction to write
274+
w.rd_wrn().clear_bit();
275+
// Software end mode
276+
w.autoend().clear_bit();
277+
w.reload().clear_bit();
278+
// Start transfer
279+
w.start().set_bit()
283280
});
284281
let mut idx = 0;
285282
// Wait until we are allowed to send data
@@ -288,29 +285,28 @@ macro_rules! i2c {
288285
for byte in snd_buffer {
289286
busy_wait!(self.i2c, txis, bit_is_set, idx, sndlen);
290287
// Put byte on the wire
291-
self.i2c.txdr().write(|w| unsafe{ w.txdata().bits(*byte) } );
288+
self.i2c.txdr().write(|w| w.txdata().set(*byte));
292289
idx += 1;
293290
}
294291
// Wait until the write finishes before beginning to read.
295292
let dummy = 0xFE;
296293
busy_wait!(self.i2c, tc, bit_is_set, idx, dummy );
297294

298295
// reSTART and prepare to receive bytes into `rcv_buffer`
299-
self.i2c.cr2().write(|w| unsafe {
300-
w
301-
// Set number of bytes to transfer
302-
.nbytes().bits(rcvlen as u8)
303-
// Set address to transfer to/from
304-
.sadd().bits((addr << 1) as u16)
305-
// 7-bit addressing mode
306-
.add10().clear_bit()
307-
// Set transfer direction to read
308-
.rd_wrn().set_bit()
309-
// Automatic end mode
310-
.autoend().set_bit()
311-
.reload().clear_bit()
312-
// Start transfer
313-
.start().set_bit()
296+
self.i2c.cr2().write(|w| {
297+
// Set number of bytes to transfer
298+
w.nbytes().set(rcvlen as u8);
299+
// Set address to transfer to/from
300+
w.sadd().set((addr << 1) as u16);
301+
// 7-bit addressing mode
302+
w.add10().clear_bit();
303+
// Set transfer direction to read
304+
w.rd_wrn().set_bit();
305+
// Automatic end mode
306+
w.autoend().set_bit();
307+
w.reload().clear_bit();
308+
// Start transfer
309+
w.start().set_bit()
314310
});
315311

316312
idx = 0;
@@ -336,19 +332,18 @@ macro_rules! i2c {
336332
// This could be up to 50% of a bus cycle (ie. up to 0.5/freq)
337333
while self.i2c.cr2().read().start().bit_is_set() {};
338334

339-
self.i2c.cr2().modify(|_, w| unsafe {
340-
w
341-
// Start transfer
342-
.start().set_bit()
343-
// Set number of bytes to transfer
344-
.nbytes().bits(buflen as u8)
345-
// Set address to transfer to/from
346-
.sadd().bits((addr << 1) as u16)
347-
// Set transfer direction to write
348-
.rd_wrn().clear_bit()
349-
// Automatic end mode
350-
.autoend().set_bit()
351-
.reload().clear_bit()
335+
self.i2c.cr2().modify(|_, w| {
336+
// Start transfer
337+
w.start().set_bit();
338+
// Set number of bytes to transfer
339+
w.nbytes().set(buflen as u8);
340+
// Set address to transfer to/from
341+
w.sadd().set((addr << 1) as u16);
342+
// Set transfer direction to write
343+
w.rd_wrn().clear_bit();
344+
// Automatic end mode
345+
w.autoend().set_bit();
346+
w.reload().clear_bit()
352347
});
353348

354349
let mut idx = 0;
@@ -358,7 +353,7 @@ macro_rules! i2c {
358353

359354
// Put byte on the wire
360355
if idx < buflen {
361-
self.i2c.txdr().write(|w| unsafe { w.txdata().bits(bytes[idx]) } );
356+
self.i2c.txdr().write(|w| w.txdata().set(bytes[idx]));
362357
idx += 1;
363358
}
364359
}
@@ -382,19 +377,18 @@ macro_rules! i2c {
382377
// Set START and prepare to receive bytes into `buffer`.
383378
// The START bit can be set even if the bus
384379
// is BUSY or I2C is in slave mode.
385-
self.i2c.cr2().modify(|_, w| unsafe {
386-
w
387-
// Start transfer
388-
.start().set_bit()
389-
// Set number of bytes to transfer
390-
.nbytes().bits(buflen as u8)
391-
// Set address to transfer to/from
392-
.sadd().bits((addr << 1) as u16)
393-
// Set transfer direction to read
394-
.rd_wrn().set_bit()
395-
// automatic end mode
396-
.autoend().set_bit()
397-
.reload().clear_bit()
380+
self.i2c.cr2().modify(|_, w| {
381+
// Start transfer
382+
w.start().set_bit();
383+
// Set number of bytes to transfer
384+
w.nbytes().set(buflen as u8);
385+
// Set address to transfer to/from
386+
w.sadd().set((addr << 1) as u16);
387+
// Set transfer direction to read
388+
w.rd_wrn().set_bit();
389+
// automatic end mode
390+
w.autoend().set_bit();
391+
w.reload().clear_bit()
398392
});
399393
let mut idx = 0;
400394
loop {
@@ -449,9 +443,9 @@ macro_rules! i2c {
449443
assert!(buflen < 256 && buflen > 0);
450444

451445
// Set the nbytes and prepare to send bytes into `buffer`.
452-
self.i2c.cr2().modify(|_, w| unsafe {
453-
w.nbytes().bits( buflen as u8)
454-
.reload().clear_bit()
446+
self.i2c.cr2().modify(|_, w| {
447+
w.nbytes().set( buflen as u8);
448+
w.reload().clear_bit()
455449
});
456450
// flush i2c tx register
457451
self.i2c.isr().write(|w| w.txe().set_bit());
@@ -465,13 +459,13 @@ macro_rules! i2c {
465459

466460
// Put byte on the wire
467461
if idx < buflen {
468-
self.i2c.txdr().write(|w| unsafe { w.txdata().bits(bytes[idx]) } );
462+
self.i2c.txdr().write(|w| w.txdata().set(bytes[idx]));
469463
idx += 1;
470464
} else {
471465
// we will never reach here. In case the master wants to read more than buflen
472466
// the hardware will send 0xFF
473467
// Also means that on slave side we cannot detect this error case
474-
self.i2c.txdr().write(|w| unsafe { w.txdata().bits(0x21) } );
468+
self.i2c.txdr().write(|w| w.txdata().set(0x21));
475469
}
476470
}
477471
}
@@ -482,12 +476,11 @@ macro_rules! i2c {
482476
assert!(buflen < 256 && buflen > 0);
483477

484478
// Set the nbytes START and prepare to receive bytes into `buffer`.
485-
self.i2c.cr2().modify(|_, w| unsafe {
486-
w
487-
// Set number of bytes to transfer: maximum as all incoming bytes will be ACK'ed
488-
.nbytes().bits(buflen as u8)
489-
// during sending nbytes automatically send a ACK, stretch clock after last byte
490-
.reload().set_bit()
479+
self.i2c.cr2().modify(|_, w| {
480+
// Set number of bytes to transfer: maximum as all incoming bytes will be ACK'ed
481+
w.nbytes().set(buflen as u8);
482+
// during sending nbytes automatically send a ACK, stretch clock after last byte
483+
w.reload().set_bit()
491484
});
492485
// end address phase, release clock stretching
493486
self.i2c.icr().write(|w|

‎src/serial/usart.rs‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -615,15 +615,11 @@ macro_rules! uart_full {
615615
usart.cr2().reset();
616616
usart.cr3().reset();
617617

618-
usart.cr2().write(|w| unsafe {
619-
w.stop()
620-
.bits(config.stopbits.bits())
621-
.txinv()
622-
.bit(config.inverted_tx)
623-
.rxinv()
624-
.bit(config.inverted_rx)
625-
.swap()
626-
.bit(config.swap)
618+
usart.cr2().write(|w| {
619+
w.stop().set(config.stopbits.bits());
620+
w.txinv().bit(config.inverted_tx);
621+
w.rxinv().bit(config.inverted_rx);
622+
w.swap().bit(config.swap)
627623
});
628624

629625
if let Some(timeout) = config.receiver_timeout {

‎src/spi.rs‎

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -171,19 +171,17 @@ macro_rules! spi {
171171

172172
#[rustfmt::skip]
173173
spi.cr1().write(|w| {
174-
unsafe {
175-
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition)
176-
.cpol().bit(mode.polarity == Polarity::IdleHigh)
177-
.mstr().set_bit()
178-
.br().bits(br)
179-
.lsbfirst().clear_bit()
180-
.ssm().set_bit()
181-
.ssi().set_bit()
182-
.rxonly().clear_bit()
183-
.crcl().clear_bit()
184-
.bidimode().clear_bit()
185-
.spe().set_bit()
186-
}
174+
w.cpha().bit(mode.phase == Phase::CaptureOnSecondTransition);
175+
w.cpol().bit(mode.polarity == Polarity::IdleHigh);
176+
w.mstr().set_bit();
177+
w.br().set(br);
178+
w.lsbfirst().clear_bit();
179+
w.ssm().set_bit();
180+
w.ssi().set_bit();
181+
w.rxonly().clear_bit();
182+
w.crcl().clear_bit();
183+
w.bidimode().clear_bit();
184+
w.spe().set_bit()
187185
});
188186

189187
Spi { spi, pins }

‎src/timer/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ macro_rules! timers {
172172
let psc = cycles / 0xffff;
173173
let arr = cycles / (psc + 1);
174174

175-
self.tim.psc().write(|w| unsafe { w.psc().bits(psc as u16) });
175+
self.tim.psc().write(|w| w.psc().set(psc as u16));
176176
self.tim.arr().write(|w| unsafe { w.bits(arr) });
177177

178178
// Generate an update event so that PSC and ARR values are copied into their

‎src/timer/stopwatch.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ macro_rules! stopwatches {
4040
///
4141
/// The counter frequency is equal to the input clock divided by the prescaler + 1.
4242
pub fn set_prescaler(&mut self, prescaler: u16) {
43-
self.tim.psc().write(|w| unsafe { w.psc().bits(prescaler) } );
43+
self.tim.psc().write(|w| w.psc().set(prescaler));
4444
self.tim.egr().write(|w| w.ug().set_bit());
4545
}
4646

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